cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

trans_rvb.c.inc (12899B)

      1/*
      2 * RISC-V translation routines for the Zb[abcs] Standard Extension.
      3 *
      4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
      5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
      6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
      7 *
      8 * This program is free software; you can redistribute it and/or modify it
      9 * under the terms and conditions of the GNU General Public License,
     10 * version 2 or later, as published by the Free Software Foundation.
     11 *
     12 * This program is distributed in the hope it will be useful, but WITHOUT
     13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     15 * more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along with
     18 * this program.  If not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#define REQUIRE_ZBA(ctx) do {                    \
     22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
     23        return false;                            \
     24    }                                            \
     25} while (0)
     26
     27#define REQUIRE_ZBB(ctx) do {                    \
     28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
     29        return false;                            \
     30    }                                            \
     31} while (0)
     32
     33#define REQUIRE_ZBC(ctx) do {                    \
     34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
     35        return false;                            \
     36    }                                            \
     37} while (0)
     38
     39#define REQUIRE_ZBS(ctx) do {                    \
     40    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
     41        return false;                            \
     42    }                                            \
     43} while (0)
     44
     45static void gen_clz(TCGv ret, TCGv arg1)
     46{
     47    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
     48}
     49
     50static bool trans_clz(DisasContext *ctx, arg_clz *a)
     51{
     52    REQUIRE_ZBB(ctx);
     53    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
     54}
     55
     56static void gen_ctz(TCGv ret, TCGv arg1)
     57{
     58    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
     59}
     60
     61static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
     62{
     63    REQUIRE_ZBB(ctx);
     64    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
     65}
     66
     67static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
     68{
     69    REQUIRE_ZBB(ctx);
     70    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
     71}
     72
     73static bool trans_andn(DisasContext *ctx, arg_andn *a)
     74{
     75    REQUIRE_ZBB(ctx);
     76    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
     77}
     78
     79static bool trans_orn(DisasContext *ctx, arg_orn *a)
     80{
     81    REQUIRE_ZBB(ctx);
     82    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
     83}
     84
     85static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
     86{
     87    REQUIRE_ZBB(ctx);
     88    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
     89}
     90
     91static bool trans_min(DisasContext *ctx, arg_min *a)
     92{
     93    REQUIRE_ZBB(ctx);
     94    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
     95}
     96
     97static bool trans_max(DisasContext *ctx, arg_max *a)
     98{
     99    REQUIRE_ZBB(ctx);
    100    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
    101}
    102
    103static bool trans_minu(DisasContext *ctx, arg_minu *a)
    104{
    105    REQUIRE_ZBB(ctx);
    106    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
    107}
    108
    109static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
    110{
    111    REQUIRE_ZBB(ctx);
    112    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
    113}
    114
    115static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
    116{
    117    REQUIRE_ZBB(ctx);
    118    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
    119}
    120
    121static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
    122{
    123    REQUIRE_ZBB(ctx);
    124    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
    125}
    126
    127static void gen_sbop_mask(TCGv ret, TCGv shamt)
    128{
    129    tcg_gen_movi_tl(ret, 1);
    130    tcg_gen_shl_tl(ret, ret, shamt);
    131}
    132
    133static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
    134{
    135    TCGv t = tcg_temp_new();
    136
    137    gen_sbop_mask(t, shamt);
    138    tcg_gen_or_tl(ret, arg1, t);
    139
    140    tcg_temp_free(t);
    141}
    142
    143static bool trans_bset(DisasContext *ctx, arg_bset *a)
    144{
    145    REQUIRE_ZBS(ctx);
    146    return gen_shift(ctx, a, EXT_NONE, gen_bset);
    147}
    148
    149static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
    150{
    151    REQUIRE_ZBS(ctx);
    152    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
    153}
    154
    155static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
    156{
    157    TCGv t = tcg_temp_new();
    158
    159    gen_sbop_mask(t, shamt);
    160    tcg_gen_andc_tl(ret, arg1, t);
    161
    162    tcg_temp_free(t);
    163}
    164
    165static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
    166{
    167    REQUIRE_ZBS(ctx);
    168    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
    169}
    170
    171static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
    172{
    173    REQUIRE_ZBS(ctx);
    174    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
    175}
    176
    177static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
    178{
    179    TCGv t = tcg_temp_new();
    180
    181    gen_sbop_mask(t, shamt);
    182    tcg_gen_xor_tl(ret, arg1, t);
    183
    184    tcg_temp_free(t);
    185}
    186
    187static bool trans_binv(DisasContext *ctx, arg_binv *a)
    188{
    189    REQUIRE_ZBS(ctx);
    190    return gen_shift(ctx, a, EXT_NONE, gen_binv);
    191}
    192
    193static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
    194{
    195    REQUIRE_ZBS(ctx);
    196    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
    197}
    198
    199static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
    200{
    201    tcg_gen_shr_tl(ret, arg1, shamt);
    202    tcg_gen_andi_tl(ret, ret, 1);
    203}
    204
    205static bool trans_bext(DisasContext *ctx, arg_bext *a)
    206{
    207    REQUIRE_ZBS(ctx);
    208    return gen_shift(ctx, a, EXT_NONE, gen_bext);
    209}
    210
    211static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
    212{
    213    REQUIRE_ZBS(ctx);
    214    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
    215}
    216
    217static bool trans_ror(DisasContext *ctx, arg_ror *a)
    218{
    219    REQUIRE_ZBB(ctx);
    220    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
    221}
    222
    223static bool trans_rori(DisasContext *ctx, arg_rori *a)
    224{
    225    REQUIRE_ZBB(ctx);
    226    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
    227}
    228
    229static bool trans_rol(DisasContext *ctx, arg_rol *a)
    230{
    231    REQUIRE_ZBB(ctx);
    232    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
    233}
    234
    235static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
    236{
    237    REQUIRE_32BIT(ctx);
    238    REQUIRE_ZBB(ctx);
    239    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
    240}
    241
    242static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
    243{
    244    REQUIRE_64BIT(ctx);
    245    REQUIRE_ZBB(ctx);
    246    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
    247}
    248
    249static void gen_orc_b(TCGv ret, TCGv source1)
    250{
    251    TCGv  tmp = tcg_temp_new();
    252    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
    253
    254    /* Set lsb in each byte if the byte was zero. */
    255    tcg_gen_sub_tl(tmp, source1, ones);
    256    tcg_gen_andc_tl(tmp, tmp, source1);
    257    tcg_gen_shri_tl(tmp, tmp, 7);
    258    tcg_gen_andc_tl(tmp, ones, tmp);
    259
    260    /* Replicate the lsb of each byte across the byte. */
    261    tcg_gen_muli_tl(ret, tmp, 0xff);
    262
    263    tcg_temp_free(tmp);
    264}
    265
    266static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
    267{
    268    REQUIRE_ZBB(ctx);
    269    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
    270}
    271
    272#define GEN_SHADD(SHAMT)                                       \
    273static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
    274{                                                              \
    275    TCGv t = tcg_temp_new();                                   \
    276                                                               \
    277    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
    278    tcg_gen_add_tl(ret, t, arg2);                              \
    279                                                               \
    280    tcg_temp_free(t);                                          \
    281}
    282
    283GEN_SHADD(1)
    284GEN_SHADD(2)
    285GEN_SHADD(3)
    286
    287#define GEN_TRANS_SHADD(SHAMT)                                             \
    288static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
    289{                                                                          \
    290    REQUIRE_ZBA(ctx);                                                      \
    291    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
    292}
    293
    294GEN_TRANS_SHADD(1)
    295GEN_TRANS_SHADD(2)
    296GEN_TRANS_SHADD(3)
    297
    298static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
    299{
    300    REQUIRE_32BIT(ctx);
    301    REQUIRE_ZBB(ctx);
    302    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
    303}
    304
    305static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
    306{
    307    REQUIRE_64BIT(ctx);
    308    REQUIRE_ZBB(ctx);
    309    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
    310}
    311
    312static void gen_clzw(TCGv ret, TCGv arg1)
    313{
    314    TCGv t = tcg_temp_new();
    315    tcg_gen_shli_tl(t, arg1, 32);
    316    tcg_gen_clzi_tl(ret, t, 32);
    317    tcg_temp_free(t);
    318}
    319
    320static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
    321{
    322    REQUIRE_64BIT(ctx);
    323    REQUIRE_ZBB(ctx);
    324    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
    325}
    326
    327static void gen_ctzw(TCGv ret, TCGv arg1)
    328{
    329    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
    330    tcg_gen_ctzi_tl(ret, ret, 64);
    331}
    332
    333static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
    334{
    335    REQUIRE_64BIT(ctx);
    336    REQUIRE_ZBB(ctx);
    337    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
    338}
    339
    340static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
    341{
    342    REQUIRE_64BIT(ctx);
    343    REQUIRE_ZBB(ctx);
    344    ctx->w = true;
    345    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
    346}
    347
    348static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
    349{
    350    TCGv_i32 t1 = tcg_temp_new_i32();
    351    TCGv_i32 t2 = tcg_temp_new_i32();
    352
    353    /* truncate to 32-bits */
    354    tcg_gen_trunc_tl_i32(t1, arg1);
    355    tcg_gen_trunc_tl_i32(t2, arg2);
    356
    357    tcg_gen_rotr_i32(t1, t1, t2);
    358
    359    /* sign-extend 64-bits */
    360    tcg_gen_ext_i32_tl(ret, t1);
    361
    362    tcg_temp_free_i32(t1);
    363    tcg_temp_free_i32(t2);
    364}
    365
    366static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
    367{
    368    REQUIRE_64BIT(ctx);
    369    REQUIRE_ZBB(ctx);
    370    ctx->w = true;
    371    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
    372}
    373
    374static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
    375{
    376    REQUIRE_64BIT(ctx);
    377    REQUIRE_ZBB(ctx);
    378    ctx->w = true;
    379    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
    380}
    381
    382static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
    383{
    384    TCGv_i32 t1 = tcg_temp_new_i32();
    385    TCGv_i32 t2 = tcg_temp_new_i32();
    386
    387    /* truncate to 32-bits */
    388    tcg_gen_trunc_tl_i32(t1, arg1);
    389    tcg_gen_trunc_tl_i32(t2, arg2);
    390
    391    tcg_gen_rotl_i32(t1, t1, t2);
    392
    393    /* sign-extend 64-bits */
    394    tcg_gen_ext_i32_tl(ret, t1);
    395
    396    tcg_temp_free_i32(t1);
    397    tcg_temp_free_i32(t2);
    398}
    399
    400static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
    401{
    402    REQUIRE_64BIT(ctx);
    403    REQUIRE_ZBB(ctx);
    404    ctx->w = true;
    405    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
    406}
    407
    408#define GEN_SHADD_UW(SHAMT)                                       \
    409static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
    410{                                                                 \
    411    TCGv t = tcg_temp_new();                                      \
    412                                                                  \
    413    tcg_gen_ext32u_tl(t, arg1);                                   \
    414                                                                  \
    415    tcg_gen_shli_tl(t, t, SHAMT);                                 \
    416    tcg_gen_add_tl(ret, t, arg2);                                 \
    417                                                                  \
    418    tcg_temp_free(t);                                             \
    419}
    420
    421GEN_SHADD_UW(1)
    422GEN_SHADD_UW(2)
    423GEN_SHADD_UW(3)
    424
    425#define GEN_TRANS_SHADD_UW(SHAMT)                             \
    426static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
    427                                    arg_sh##SHAMT##add_uw *a) \
    428{                                                             \
    429    REQUIRE_64BIT(ctx);                                       \
    430    REQUIRE_ZBA(ctx);                                         \
    431    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
    432}
    433
    434GEN_TRANS_SHADD_UW(1)
    435GEN_TRANS_SHADD_UW(2)
    436GEN_TRANS_SHADD_UW(3)
    437
    438static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
    439{
    440    TCGv t = tcg_temp_new();
    441    tcg_gen_ext32u_tl(t, arg1);
    442    tcg_gen_add_tl(ret, t, arg2);
    443    tcg_temp_free(t);
    444}
    445
    446static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
    447{
    448    REQUIRE_64BIT(ctx);
    449    REQUIRE_ZBA(ctx);
    450    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
    451}
    452
    453static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
    454{
    455    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
    456}
    457
    458static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
    459{
    460    REQUIRE_64BIT(ctx);
    461    REQUIRE_ZBA(ctx);
    462    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
    463}
    464
    465static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
    466{
    467    REQUIRE_ZBC(ctx);
    468    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
    469}
    470
    471static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
    472{
    473     gen_helper_clmulr(dst, src1, src2);
    474     tcg_gen_shri_tl(dst, dst, 1);
    475}
    476
    477static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
    478{
    479    REQUIRE_ZBC(ctx);
    480    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
    481}
    482
    483static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
    484{
    485    REQUIRE_ZBC(ctx);
    486    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
    487}