core-isa.h (24842B)
1/* 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3 * processor CORE configuration 4 * 5 * See <xtensa/config/core.h>, which includes this file, for more details. 6 */ 7 8/* Xtensa processor core configuration information. 9 10 Copyright (c) 1999-2010 Tensilica Inc. 11 12 Permission is hereby granted, free of charge, to any person obtaining 13 a copy of this software and associated documentation files (the 14 "Software"), to deal in the Software without restriction, including 15 without limitation the rights to use, copy, modify, merge, publish, 16 distribute, sublicense, and/or sell copies of the Software, and to 17 permit persons to whom the Software is furnished to do so, subject to 18 the following conditions: 19 20 The above copyright notice and this permission notice shall be included 21 in all copies or substantial portions of the Software. 22 23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30 31#ifndef XTENSA_DC233C_CORE_ISA_H 32#define XTENSA_DC233C_CORE_ISA_H 33 34/**************************************************************************** 35 Parameters Useful for Any Code, USER or PRIVILEGED 36 ****************************************************************************/ 37 38/* 39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 40 * configured, and a value of 0 otherwise. These macros are always defined. 41 */ 42 43 44/*---------------------------------------------------------------------- 45 ISA 46 ----------------------------------------------------------------------*/ 47 48#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 49#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 50#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 51#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 52#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 53#define XCHAL_HAVE_DEBUG 1 /* debug option */ 54#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 55#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 56#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 57#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 58#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 59#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 60#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 61#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 62#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 63#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 64#define XCHAL_HAVE_L32R 1 /* L32R instruction */ 65#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 66#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 67#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 68#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 69#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 70#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 71#define XCHAL_HAVE_ABS 1 /* ABS instruction */ 72/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 73/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 74#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 75#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 76#define XCHAL_HAVE_SPECULATION 0 /* speculation */ 77#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 78#define XCHAL_NUM_CONTEXTS 1 /* */ 79#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 80#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 81#define XCHAL_HAVE_PRID 1 /* processor ID register */ 82#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 83#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 84#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 85#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 86#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 87#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 88#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 89#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 90#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 91#define XCHAL_HAVE_FP 0 /* floating point pkg */ 92#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 93#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 94#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 95#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 96#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 97#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 98#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 99#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 100#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 101#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 102#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 103#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 104#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 105#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 106#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 107#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 108#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 109 110 111/*---------------------------------------------------------------------- 112 MISC 113 ----------------------------------------------------------------------*/ 114 115#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 116#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 117#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 118/* In T1050, applies to selected core load and store instructions (see ISA): */ 119#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 120#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 121#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 122#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 123 124#define XCHAL_SW_VERSION 900001 /* sw version of this header */ 125 126#define XCHAL_CORE_ID "dc233c" /* alphanum core name 127(CoreID) set in the Xtensa 128Processor Generator */ 129 130#define XCHAL_CORE_DESCRIPTION "dc233c" 131#define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ 132 133/* 134 * These definitions describe the hardware targeted by this software. 135 */ 136#define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ 137#define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ 138#define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ 139#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ 140#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 141#define XCHAL_HW_VERSION 240001 /* major*100+minor */ 142#define XCHAL_HW_REL_LX4 1 143#define XCHAL_HW_REL_LX4_0 1 144#define XCHAL_HW_REL_LX4_0_1 1 145#define XCHAL_HW_CONFIGID_RELIABLE 1 146/* If software targets a *range* of hardware versions, these are the bounds: */ 147#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ 148#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 149#define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ 150#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ 151#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 152#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ 153 154 155/*---------------------------------------------------------------------- 156 CACHE 157 ----------------------------------------------------------------------*/ 158 159#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 160#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 161#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 162#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 163 164#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 165#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 166 167#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 168#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 169 170#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 171 172 173 174 175/**************************************************************************** 176 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 177 ****************************************************************************/ 178 179 180#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 181 182/*---------------------------------------------------------------------- 183 CACHE 184 ----------------------------------------------------------------------*/ 185 186#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 187 188/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 189 190/* Number of cache sets in log2(lines per way): */ 191#define XCHAL_ICACHE_SETWIDTH 7 192#define XCHAL_DCACHE_SETWIDTH 7 193 194/* Cache set associativity (number of ways): */ 195#define XCHAL_ICACHE_WAYS 4 196#define XCHAL_DCACHE_WAYS 4 197 198/* Cache features: */ 199#define XCHAL_ICACHE_LINE_LOCKABLE 1 200#define XCHAL_DCACHE_LINE_LOCKABLE 1 201#define XCHAL_ICACHE_ECC_PARITY 0 202#define XCHAL_DCACHE_ECC_PARITY 0 203 204/* Cache access size in bytes (affects operation of SICW instruction): */ 205#define XCHAL_ICACHE_ACCESS_SIZE 4 206#define XCHAL_DCACHE_ACCESS_SIZE 4 207 208/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 209#define XCHAL_CA_BITS 4 210 211 212/*---------------------------------------------------------------------- 213 INTERNAL I/D RAM/ROMs and XLMI 214 ----------------------------------------------------------------------*/ 215 216#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 217#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 218#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 219#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 220#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 221#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 222 223#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 224 225 226/*---------------------------------------------------------------------- 227 INTERRUPTS and TIMERS 228 ----------------------------------------------------------------------*/ 229 230#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 231#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 232#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 233#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 234#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 235#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 236#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 237#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 238#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 239(not including level zero) */ 240#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 241/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 242 243/* Masks of interrupts at each interrupt level: */ 244#define XCHAL_INTLEVEL1_MASK 0x001F80FF 245#define XCHAL_INTLEVEL2_MASK 0x00000100 246#define XCHAL_INTLEVEL3_MASK 0x00200E00 247#define XCHAL_INTLEVEL4_MASK 0x00001000 248#define XCHAL_INTLEVEL5_MASK 0x00002000 249#define XCHAL_INTLEVEL6_MASK 0x00000000 250#define XCHAL_INTLEVEL7_MASK 0x00004000 251 252/* Masks of interrupts at each range 1..n of interrupt levels: */ 253#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 254#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 255#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 256#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 257#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 258#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 259#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 260 261/* Level of each interrupt: */ 262#define XCHAL_INT0_LEVEL 1 263#define XCHAL_INT1_LEVEL 1 264#define XCHAL_INT2_LEVEL 1 265#define XCHAL_INT3_LEVEL 1 266#define XCHAL_INT4_LEVEL 1 267#define XCHAL_INT5_LEVEL 1 268#define XCHAL_INT6_LEVEL 1 269#define XCHAL_INT7_LEVEL 1 270#define XCHAL_INT8_LEVEL 2 271#define XCHAL_INT9_LEVEL 3 272#define XCHAL_INT10_LEVEL 3 273#define XCHAL_INT11_LEVEL 3 274#define XCHAL_INT12_LEVEL 4 275#define XCHAL_INT13_LEVEL 5 276#define XCHAL_INT14_LEVEL 7 277#define XCHAL_INT15_LEVEL 1 278#define XCHAL_INT16_LEVEL 1 279#define XCHAL_INT17_LEVEL 1 280#define XCHAL_INT18_LEVEL 1 281#define XCHAL_INT19_LEVEL 1 282#define XCHAL_INT20_LEVEL 1 283#define XCHAL_INT21_LEVEL 3 284#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 285#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 286#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 287EXCSAVE/EPS/EPC_n, RFI n) */ 288 289/* Type of each interrupt: */ 290#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 291#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 292#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 293#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 294#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 295#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 296#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 297#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 298#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 299#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 300#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 301#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 302#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 303#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 304#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 305#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 306#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 307#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 308#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 309#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 310#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 311#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 312 313/* Masks of interrupts for each type of interrupt: */ 314#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 315#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 316#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 317#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 318#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 319#define XCHAL_INTTYPE_MASK_NMI 0x00004000 320#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 321 322/* Interrupt numbers assigned to specific interrupt sources: */ 323#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 324#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 325#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 326#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 327#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 328 329/* Interrupt numbers for levels at which only one interrupt is configured: */ 330#define XCHAL_INTLEVEL2_NUM 8 331#define XCHAL_INTLEVEL4_NUM 12 332#define XCHAL_INTLEVEL5_NUM 13 333#define XCHAL_INTLEVEL7_NUM 14 334/* (There are many interrupts each at level(s) 1, 3.) */ 335 336 337/* 338 * External interrupt vectors/levels. 339 * These macros describe how Xtensa processor interrupt numbers 340 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 341 * map to external BInterrupt<n> pins, for those interrupts 342 * configured as external (level-triggered, edge-triggered, or NMI). 343 * See the Xtensa processor databook for more details. 344 */ 345 346/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 347#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 348#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 349#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 350#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 351#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 352#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 353#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 354#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 355#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 356#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 357#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 358#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 359#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 360#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 361#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 362#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 363#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 364 365 366/*---------------------------------------------------------------------- 367 EXCEPTIONS and VECTORS 368 ----------------------------------------------------------------------*/ 369 370#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 371number: 1 == XEA1 (old) 3722 == XEA2 (new) 3730 == XEAX (extern) or TX */ 374#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 375#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 376#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 377#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 378#define XCHAL_HAVE_HALT 0 /* halt architecture option */ 379#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 380#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 381#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 382#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 383#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 384#define XCHAL_VECBASE_RESET_PADDR 0x00002000 385#define XCHAL_RESET_VECBASE_OVERLAP 0 386 387#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 388#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 389#define XCHAL_RESET_VECTOR1_VADDR 0x00001000 390#define XCHAL_RESET_VECTOR1_PADDR 0x00001000 391#define XCHAL_RESET_VECTOR_VADDR 0xFE000000 392#define XCHAL_RESET_VECTOR_PADDR 0xFE000000 393#define XCHAL_USER_VECOFS 0x00000340 394#define XCHAL_USER_VECTOR_VADDR 0x00002340 395#define XCHAL_USER_VECTOR_PADDR 0x00002340 396#define XCHAL_KERNEL_VECOFS 0x00000300 397#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 398#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 399#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 400#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 401#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 402#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 403#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 404#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 405#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 406#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 407#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 408#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 409#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 410#define XCHAL_INTLEVEL2_VECOFS 0x00000180 411#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 412#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 413#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 414#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 415#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 416#define XCHAL_INTLEVEL4_VECOFS 0x00000200 417#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 418#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 419#define XCHAL_INTLEVEL5_VECOFS 0x00000240 420#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 421#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 422#define XCHAL_INTLEVEL6_VECOFS 0x00000280 423#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 424#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 425#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 426#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 427#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 428#define XCHAL_NMI_VECOFS 0x000002C0 429#define XCHAL_NMI_VECTOR_VADDR 0x000022C0 430#define XCHAL_NMI_VECTOR_PADDR 0x000022C0 431#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 432#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 433#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 434 435 436/*---------------------------------------------------------------------- 437 DEBUG 438 ----------------------------------------------------------------------*/ 439 440#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 441#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 442#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 443#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 444 445 446/*---------------------------------------------------------------------- 447 MMU 448 ----------------------------------------------------------------------*/ 449 450/* See core-matmap.h header file for more details. */ 451 452#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 453#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 454#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 455#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 456#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 457#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 458#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 459#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 460[autorefill] and protection) 461usable for an MMU-based OS */ 462/* If none of the above last 4 are set, it's a custom TLB configuration. */ 463#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 464#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 465 466#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 467#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 468#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 469 470#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 471 472 473#endif /* XTENSA_DC233C_CORE_ISA_H */