cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-str.h (946B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define i386 target-specific operand constraints.
      4 * Copyright (c) 2021 Linaro
      5 *
      6 */
      7
      8/*
      9 * Define constraint letters for register sets:
     10 * REGS(letter, register_mask)
     11 */
     12REGS('a', 1u << TCG_REG_EAX)
     13REGS('b', 1u << TCG_REG_EBX)
     14REGS('c', 1u << TCG_REG_ECX)
     15REGS('d', 1u << TCG_REG_EDX)
     16REGS('S', 1u << TCG_REG_ESI)
     17REGS('D', 1u << TCG_REG_EDI)
     18
     19REGS('r', ALL_GENERAL_REGS)
     20REGS('x', ALL_VECTOR_REGS)
     21REGS('q', ALL_BYTEL_REGS)     /* regs that can be used as a byte operand */
     22REGS('Q', ALL_BYTEH_REGS)     /* regs with a second byte (e.g. %ah) */
     23REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
     24REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)    /* qemu_st8_i32 data */
     25
     26/*
     27 * Define constraint letters for constants:
     28 * CONST(letter, TCG_CT_CONST_* bit set)
     29 */
     30CONST('e', TCG_CT_CONST_S32)
     31CONST('I', TCG_CT_CONST_I32)
     32CONST('W', TCG_CT_CONST_WSZ)
     33CONST('Z', TCG_CT_CONST_U32)