cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target.opc.h (1650B)

      1/*
      2 * Copyright (c) 2019 Linaro
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a copy
      5 * of this software and associated documentation files (the "Software"), to deal
      6 * in the Software without restriction, including without limitation the rights
      7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
      8 * copies of the Software, and to permit persons to whom the Software is
      9 * furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     20 * THE SOFTWARE.
     21 *
     22 * Target-specific opcodes for host vector expansion.  These will be
     23 * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
     24 * consider these to be UNSPEC with names.
     25 */
     26
     27DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
     28DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
     29DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
     30DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
     31DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
     32DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
     33DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
     34DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
     35DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)