cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-str.h (502B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define RISC-V target-specific operand constraints.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * Define constraint letters for register sets:
      9 * REGS(letter, register_mask)
     10 */
     11REGS('r', ALL_GENERAL_REGS)
     12REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
     13
     14/*
     15 * Define constraint letters for constants:
     16 * CONST(letter, TCG_CT_CONST_* bit set)
     17 */
     18CONST('I', TCG_CT_CONST_S12)
     19CONST('N', TCG_CT_CONST_N12)
     20CONST('M', TCG_CT_CONST_M12)
     21CONST('Z', TCG_CT_CONST_ZERO)