cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-set.h (720B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define Sparc target-specific constraint sets.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
      9 * Each operand should be a sequence of constraint letters as defined by
     10 * tcg-target-con-str.h; the constraint combination is inclusive or.
     11 */
     12C_O0_I1(r)
     13C_O0_I2(rZ, r)
     14C_O0_I2(RZ, r)
     15C_O0_I2(rZ, rJ)
     16C_O0_I2(RZ, RJ)
     17C_O0_I2(sZ, A)
     18C_O0_I2(SZ, A)
     19C_O1_I1(r, A)
     20C_O1_I1(R, A)
     21C_O1_I1(r, r)
     22C_O1_I1(r, R)
     23C_O1_I1(R, r)
     24C_O1_I1(R, R)
     25C_O1_I2(R, R, R)
     26C_O1_I2(r, rZ, rJ)
     27C_O1_I2(R, RZ, RJ)
     28C_O1_I4(r, rZ, rJ, rI, 0)
     29C_O1_I4(R, RZ, RJ, RI, 0)
     30C_O2_I2(r, r, rZ, rJ)
     31C_O2_I4(R, R, RZ, RZ, RJ, RI)
     32C_O2_I4(r, r, rZ, rZ, rJ, rJ)