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| * | hw/dma: sifive_pdma: Fix Control.claim bit detectionBin Meng2021-10-071-1/+1
| * | hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUARTPhilippe Mathieu-Daudé2021-10-072-16/+93
| * | hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion containerPhilippe Mathieu-Daudé2021-10-072-3/+9
| * | hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definitionPhilippe Mathieu-Daudé2021-10-072-8/+10
| * | hw/char: sifive_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| * | hw/char: shakti_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| * | hw/char: ibex_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| * | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-072-13/+21
| * | disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich2021-10-071-3/+154
| * | target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-073-33/+0
| * | target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-072-77/+21
| * | target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-074-79/+15
| * | target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
| * | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-074-55/+18
| * | target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-072-41/+50
| * | target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-074-1/+65
| * | target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-072-18/+24
| * | target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-072-78/+0
| * | target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-072-63/+0
| * | target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-072-13/+23
| * | target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-072-0/+8
| * | target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
| * | target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
| * | target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
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* | Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into stagingRichard Henderson2021-10-069-58/+185
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| * | target/hexagon: Use tcg_constant_*Philippe Mathieu-Daudé2021-10-065-53/+25
| * | target/hexagon: Remove unused TCG temporary from predicated loadsPhilippe Mathieu-Daudé2021-10-061-2/+0
| * | Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson2021-10-065-3/+160
* | | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211006' into stagingRichard Henderson2021-10-0644-610/+1445
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| * | | tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vecRichard Henderson2021-10-051-1/+23
| * | | tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson2021-10-053-1/+22
| * | | tcg/s390x: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2021-10-052-0/+66
| * | | tcg/s390x: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2021-10-052-1/+26
| * | | tcg/s390x: Implement vector shift operationsRichard Henderson2021-10-053-7/+99
| * | | tcg/s390x: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2021-10-052-1/+8
| * | | tcg/s390x: Implement andc, orc, abs, neg, not vector operationsRichard Henderson2021-10-053-5/+39
| * | | tcg/s390x: Implement minimal vector operationsRichard Henderson2021-10-051-4/+150
| * | | tcg/s390x: Implement tcg_out_dup*_vecRichard Henderson2021-10-051-3/+119
| * | | tcg/s390x: Implement tcg_out_mov for vector typesRichard Henderson2021-10-051-4/+68
| * | | tcg/s390x: Implement tcg_out_ld/st for vector typesRichard Henderson2021-10-051-12/+120
| * | | tcg/s390x: Add host vector frameworkRichard Henderson2021-10-055-5/+184
| * | | tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGRegRichard Henderson2021-10-051-21/+7
| * | | tcg/s390x: Change FACILITY representationRichard Henderson2021-10-052-51/+52
| * | | tcg/s390x: Rename from tcg/s390Richard Henderson2021-10-055-2/+0
| * | | tcg: Expand usadd/ussub with umin/umaxRichard Henderson2021-10-051-2/+35
| * | | hw/core/cpu: Re-sort the non-pointers to the end of CPUClassRichard Henderson2021-10-051-4/+7
| * | | trace: Split guest_mem_beforeRichard Henderson2021-10-057-122/+28
| * | | plugins: Reorg arguments to qemu_plugin_vcpu_mem_cbRichard Henderson2021-10-058-53/+82
| * | | accel/tcg: Pass MemOpIdx to atomic_trace_*_postRichard Henderson2021-10-052-39/+39
| * | | trace/mem: Pass MemOpIdx to trace_mem_get_infoRichard Henderson2021-10-055-51/+49
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-02-10 03:40:31 +0000