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* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into stagingRichard Henderson2021-09-2434-315/+119
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| * tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson2021-09-211-8/+2
| * hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-2112-21/+23
| * tcg/sparc: Introduce tcg_out_mov_delayRichard Henderson2021-09-211-6/+15
| * tcg/sparc: Drop inline markersRichard Henderson2021-09-211-23/+22
| * tcg/mips: Drop special alignment for code_gen_bufferRichard Henderson2021-09-211-91/+0
| * tcg/mips: Unset TCG_TARGET_HAS_direct_jumpRichard Henderson2021-09-212-25/+10
| * tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subrRichard Henderson2021-09-211-2/+4
| * tcg/mips: Drop inline markersRichard Henderson2021-09-211-49/+27
| * accel/tcg: Restrict cpu_handle_halt() to sysemuPhilippe Mathieu-Daudé2021-09-211-2/+4
| * include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-2122-89/+13
* | Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.2-pull-re...Peter Maydell2021-09-244-69/+46
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| * | linux-user/aarch64: Use force_sig_fault()Peter Maydell2021-09-231-25/+8
| * | linux-user/arm: Use force_sig_fault()Peter Maydell2021-09-231-38/+15
| * | linux-user: Provide new force_sig_fault() functionPeter Maydell2021-09-232-0/+18
| * | linux-user: Zero out target_siginfo_t in force_sig()Peter Maydell2021-09-231-1/+1
| * | linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPEPeter Maydell2021-09-231-7/+4
| * | linux-user/arm: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
| * | linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
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* | Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into ...Peter Maydell2021-09-243-13/+25
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| * hw/nvme: Return error for fused operationsPankaj Raghav2021-09-241-0/+8
| * hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar2021-09-242-3/+17
| * hw/nvme: fix validation of ASQ and ACQKlaus Jensen2021-09-242-10/+0
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* Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson2021-09-2134-669/+1844
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| * hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
| * target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-212-16/+16
| * target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
| * docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng2021-09-211-23/+26
| * hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang2021-09-211-6/+6
| * hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan2021-09-211-6/+10
| * hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang2021-09-211-0/+9
| * hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang2021-09-211-0/+19
| * hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-213-1/+124
| * hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-211-200/+327
| * hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-218-156/+339
| * hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-2111-15/+15
| * sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-214-2/+69
| * hw/timer: Add SiFive PWM supportAlistair Francis2021-09-215-0/+540
| * hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-213-5/+17
| * hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-217-12/+33
| * hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-213-11/+16
| * hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis2021-09-212-20/+50
| * target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis2021-09-211-0/+30
| * target/riscv: Fix satp writeLIU Zhiwei2021-09-211-1/+1
| * target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-212-2/+3
* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell2021-09-2124-168/+1825
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| * | target/arm: Optimize MVE 1op-immediate insnsPeter Maydell2021-09-211-5/+21
| * | target/arm: Optimize MVE VSLI and VSRIPeter Maydell2021-09-211-2/+2
| * | target/arm: Optimize MVE VSHLL and VMOVLPeter Maydell2021-09-211-8/+59
| * | target/arm: Optimize MVE VSHL, VSHR immediate formsPeter Maydell2021-09-211-20/+63
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