sinitax/cachepc-qemu - Fork of AMDESE/qemu with changes for cachepc side-channel attack

	Commit message (Collapse)	Author	Age	Files	Lines
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*	exec: Return CPUState from qemu_get_cpu()	Andreas Färber	2013-01-15	1	-1/+0
\| \| \| \| \| \| \|	Move the declaration to qemu/cpu.h and add documentation. The implementation still depends on CPUArchState for CPU iteration. Signed-off-by: Andreas Färber <afaerber@suse.de>
*	cpu: Move cpu_index field to CPUState	Andreas Färber	2013-01-15	2	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \|	Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
*	cpu: Move numa_node field to CPUState	Andreas Färber	2013-01-15	1	-1/+0
\| \| \| \|	Signed-off-by: Andreas Färber <afaerber@suse.de>
*	cpu: Move nr_{cores,threads} fields to CPUState	Andreas Färber	2013-01-15	1	-2/+0
\| \| \| \| \| \| \| \|	To facilitate the field movements, pass MIPSCPU to malta_mips_config(); avoid that for mips_cpu_map_tc() since callers only access MIPS Thread Contexts, inside TCG helpers. Signed-off-by: Andreas Färber <afaerber@suse.de>
*	Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu	Andreas Färber	2012-12-23	2	-7/+13
\| \| \| \| \| \|	Adapt header include paths. Signed-off-by: Andreas Färber <afaerber@suse.de>
*	memory: introduce memory_region_test_and_clear_dirty	Juan Quintela	2012-12-20	1	-0/+16
\| \| \| \| \| \| \|	This function avoids having to do two calls, one to test the dirty bit, and other to reset it. Signed-off-by: Juan Quintela <quintela@redhat.com>
*	protect the ramlist with a separate mutex	Umesh Deshpande	2012-12-20	1	-0/+9
\| \| \| \| \| \| \| \| \| \| \| \|	Add the new mutex that protects shared state between ram_save_live and the iothread. If the iothread mutex has to be taken together with the ramlist mutex, the iothread shall always be _outside_. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Umesh Deshpande <udeshpan@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
*	add a version number to ram_list	Umesh Deshpande	2012-12-20	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \|	This will be used to detect if last_block might have become invalid across different calls to ram_save_live. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Umesh Deshpande <udeshpan@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
*	exec: change RAM list to a TAILQ	Paolo Bonzini	2012-12-20	1	-2/+2
\| \| \| \| \|	Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
*	exec: change ramlist from MRU order to a 1-item cache	Paolo Bonzini	2012-12-20	1	-0/+1
\| \| \| \| \| \| \| \| \|	Most of the time, only 2 items will be active (from/to for a string operation, or code/data). But TCG guests likely won't have gigabytes of memory, so this actually goes down to 1 item. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
*	misc: move include files to include/qemu/	Paolo Bonzini	2012-12-19	7	-10/+10
\| \| \| \|	Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
*	exec: move include files to include/exec/	Paolo Bonzini	2012-12-19	23	-0/+4065
	Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>