1 files changed, 79 insertions, 58 deletions

diff --git a/src/cachepc.h b/src/cachepc.h
index 72c348b..8c73249 100755
--- a/src/cachepc.h
+++ b/src/cachepc.h
@@ -3,22 +3,28 @@
 #include <linux/kernel.h>
 #include <linux/types.h> 
 #include <linux/slab.h>
+#include <linux/delay.h>
 
 #include "asm.h"
 #include "cache_types.h"
 #include "util.h"
 
-#define L2_HIT_CNTR 0xC0010201
-#define L2_MISS_CNTR 0xC0010203
+#define L2_MISS_CNTR 0xC0010201
+#define L2_HIT_CNTR 0xC0010203
 
 void cachepc_init_counters(void);
 
 cache_ctx *cachepc_get_ctx(cache_level cl);
+void cachepc_release_ctx(cache_ctx *ctx);
+
 cacheline *cachepc_prepare_ds(cache_ctx *ctx);
+void cachepc_release_ds(cache_ctx *ctx, cacheline *ds);
+
+cacheline *cachepc_prepare_victim(cache_ctx *ctx, uint32_t set);
+void cachepc_release_victim(cache_ctx *ctx, cacheline *ptr);
+
 void cachepc_save_msrmts(cacheline *head);
 void cachepc_print_msrmts(cacheline *head);
-void cachepc_release_ds(cache_ctx *ctx, cacheline *ds);
-void cachepc_release_ctx(cache_ctx *ctx);
 
 __attribute__((always_inline))
 static inline cacheline *cachepc_prime(cacheline *head);
@@ -26,20 +32,23 @@ static inline cacheline *cachepc_prime(cacheline *head);
 __attribute__((always_inline))
 static inline cacheline *cachepc_prime_rev(cacheline *head);
 
-__attribute__((always_inline))
-static inline cacheline *cachepc_probe_set(cacheline *curr_cl);
+//__attribute__((always_inline))
+//static inline cacheline *cachepc_probe_set(cacheline *curr_cl);
 
 __attribute__((always_inline))
 static inline cacheline *cachepc_probe(cacheline *head);
 
-extern uint8_t *cachepc_msrmts;
+extern uint16_t *cachepc_msrmts;
 extern size_t cachepc_msrmts_count;
 
+extern cache_ctx *cachepc_ctx;
+extern cacheline *cachepc_ds;
+
 /*
  * Prime phase: fill the target cache (encoded in the size of the data structure)
  * with the prepared data structure, i.e. with attacker data.
  */
-static inline cacheline *
+cacheline *
 cachepc_prime(cacheline *head)
 {
     cacheline *curr_cl;
@@ -73,7 +82,7 @@ cachepc_prime(cacheline *head)
  *             A) An evicted set is L2_ACCESS_TIME - L1_ACCESS_TIME slower
  *             B) An evicted set is L3_ACCESS_TIME - L2_ACCESS_TIME slower
  */
-static inline cacheline *
+cacheline *
 cachepc_prime_rev(cacheline *head)
 {
     cacheline *curr_cl;
@@ -89,61 +98,73 @@ cachepc_prime_rev(cacheline *head)
     return curr_cl->prev;
 }
 
-static inline cacheline *
-cachepc_probe_set(cacheline *curr_cl)
+cacheline *
+cachepc_probe(cacheline *start_cl)
 {
 	uint64_t pre1, pre2;
 	uint64_t post1, post2;
 	cacheline *next_cl;
+	cacheline *curr_cl;
 
-	pre1 = cachepc_readpmc(L2_HIT_CNTR);
-	pre2 = cachepc_readpmc(L2_MISS_CNTR);
-
-	cachepc_mfence();
-	asm volatile(
-		"mov 8(%[curr_cl]), %%rax \n\t"              // +8
-		"mov 8(%%rax), %%rcx \n\t"                   // +16
-		"mov 8(%%rcx), %%rax \n\t"                   // +24
-		"mov 8(%%rax), %%rcx \n\t"                   // +32
-		"mov 8(%%rcx), %%rax \n\t"                   // +40
-		"mov 8(%%rax), %%rcx \n\t"                   // +48
-		"mov 8(%%rcx), %[curr_cl_out] \n\t"          // +56
-		"mov 8(%[curr_cl_out]), %[next_cl_out] \n\t" // +64
-		: [next_cl_out] "=r" (next_cl),
-		  [curr_cl_out] "=r" (curr_cl)
-		: [curr_cl] "r" (curr_cl)
-		: "rax", "rcx"
-	);
-	cachepc_mfence();
-	cachepc_cpuid();
-
-	post1 = cachepc_readpmc(L2_HIT_CNTR);
-	cachepc_cpuid();
-	post2 = cachepc_readpmc(L2_MISS_CNTR);
-	cachepc_cpuid();
-
-	/* works across size boundary */
-	curr_cl->count = 0;
-	curr_cl->count += post1 - pre1;
-	curr_cl->count += post2 - pre2;
-
-	return next_cl;
-}
+	curr_cl = start_cl;
 
-static inline cacheline *
-cachepc_probe(cacheline *head)
-{
-	cacheline *curr_cs;
-
-	//printk(KERN_WARNING "CachePC: Probing..");
-       
-	curr_cs = head;
 	do {
-		curr_cs = cachepc_probe_set(curr_cs);
-	} while (__builtin_expect(curr_cs != head, 1));
-
-	//printk(KERN_WARNING "CachePC: Probing done");
-
-	return curr_cs->next;
+		cachepc_cpuid();
+		cachepc_mfence();
+	
+		asm volatile(
+			"mov 8(%[curr_cl]), %%rax \n\t"              // +8
+			"mov 8(%%rax), %%rcx \n\t"                   // +16
+			"mov 8(%%rcx), %%rax \n\t"                   // +24
+			"mov 8(%%rax), %%rcx \n\t"                   // +32
+			"mov 8(%%rcx), %%rax \n\t"                   // +40
+			"mov 8(%%rax), %%rcx \n\t"                   // +48
+			"mov 8(%%rcx), %[curr_cl_out] \n\t"          // +56
+			"mov 8(%[curr_cl_out]), %[next_cl_out] \n\t" // +64
+			: [next_cl_out] "=r" (next_cl),
+			  [curr_cl_out] "=r" (curr_cl)
+			: [curr_cl] "r" (curr_cl)
+			: "rax", "rcx"
+		);
+
+		cachepc_cpuid();
+		cachepc_mfence();
+
+		pre1 = cachepc_readpmc(L2_HIT_CNTR);
+		pre2 = cachepc_readpmc(L2_MISS_CNTR);
+
+		cachepc_cpuid();
+		cachepc_mfence();
+
+		msleep(100);
+
+		post1 = cachepc_readpmc(L2_HIT_CNTR);
+		cachepc_cpuid();
+		post2 = cachepc_readpmc(L2_MISS_CNTR);
+		cachepc_cpuid();
+
+		/* works across size boundary */
+		curr_cl->count = 0;
+		curr_cl->count += post1 - pre1;
+		curr_cl->count += post2 - pre2;
+	} while (__builtin_expect(curr_cl != start_cl, 1));
+
+	return curr_cl->next;
 }
 
+// static inline cacheline *
+// cachepc_probe(cacheline *head)
+// {
+// 	cacheline *curr_cs;
+// 
+// 	//printk(KERN_WARNING "CachePC: Probing..");
+//        
+// 	curr_cs = head;
+// 	do {
+// 		curr_cs = cachepc_probe_set(curr_cs);
+// 	} while (__builtin_expect(curr_cs != head, 1));
+// 
+// 	//printk(KERN_WARNING "CachePC: Probing done");
+// 
+// 	return curr_cs->next;
+// }