From 98babf91dcf166bc7644a3d70a90dac272f12a75 Mon Sep 17 00:00:00 2001
From: Louis Burda <quent.burda@gmail.com>
Date: Sat, 13 Aug 2022 16:44:04 +0200
Subject: Reorder repo into module and tests

---
 kmod/asm.h | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100755 kmod/asm.h

(limited to 'kmod/asm.h')

diff --git a/kmod/asm.h b/kmod/asm.h
new file mode 100755
index 0000000..35f803b
--- /dev/null
+++ b/kmod/asm.h
@@ -0,0 +1,85 @@
+#pragma once
+
+#include <linux/kernel.h>
+
+#define CPUID_AFFECTED_REGS "rax", "rbx", "rcx", "rdx"
+
+__attribute__((always_inline))
+static inline uint64_t cachepc_readpmc(uint64_t event);
+
+__attribute__((always_inline))
+static inline void cachepc_cpuid(void);
+
+__attribute__((always_inline))
+static inline void cachepc_lfence(void);
+
+__attribute__((always_inline))
+static inline void cachepc_sfence(void);
+
+__attribute__((always_inline))
+static inline void cachepc_mfence(void);
+
+__attribute__((always_inline))
+static inline void cachepc_readq(void *p);
+
+uint64_t
+cachepc_readpmc(uint64_t event)
+{
+	uint32_t lo, hi;
+
+	event = 0xC0010201 + 2 * event;
+
+	asm volatile (
+		"rdmsr"
+		: "=a" (lo), "=d" (hi)
+		: "c"(event)
+	);
+
+	return ((uint64_t) hi << 32) | (uint64_t) lo;
+}
+
+void
+cachepc_cpuid(void)
+{
+	asm volatile(
+		"mov $0x80000005, %%eax\n\t"
+		"cpuid\n\t"
+		::: CPUID_AFFECTED_REGS
+	);
+}
+
+void
+cachepc_lfence(void)
+{
+	asm volatile(
+		"lfence\n\t"
+		::: "memory"
+	);
+}
+
+void
+cachepc_sfence(void)
+{
+	asm volatile(
+		"sfence\n\t"
+		::: "memory"
+	);
+}
+
+void
+cachepc_mfence(void)
+{
+	asm volatile(
+		"mfence\n\t"
+		::: "memory"
+	);
+}
+
+void
+cachepc_readq(void *p)
+{
+	asm volatile (
+		"movq (%0), %%r10\n\t"
+		: : "r" (p) : "r10"
+	);
+}
-- 
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