From cee2126b8f316677ebee57e19fe7d50d09c066d1 Mon Sep 17 00:00:00 2001 From: Louis Burda Date: Mon, 4 Jul 2022 16:26:35 +0200 Subject: Initial out-of-tree setup --- src/asm.h | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100755 src/asm.h (limited to 'src/asm.h') diff --git a/src/asm.h b/src/asm.h new file mode 100755 index 0000000..9509952 --- /dev/null +++ b/src/asm.h @@ -0,0 +1,72 @@ +#pragma once + +#include + +#define CPUID_AFFECTED_REGS "rax", "rbx", "rcx", "rdx" + +__attribute__((always_inline)) +static inline uint64_t cachepc_readpmc(uint64_t event); + +__attribute__((always_inline)) +static inline void cachepc_cpuid(void); + +__attribute__((always_inline)) +static inline void cachepc_lfence(void); + +__attribute__((always_inline)) +static inline void cachepc_sfence(void); + +__attribute__((always_inline)) +static inline void cachepc_mfence(void); + +uint64_t +cachepc_readpmc(uint64_t event) +{ + uint32_t lo, hi; + + asm volatile ( + "mov %[event], %%rcx\t\n" + "rdpmc\t\n" + : "=a" (lo), "=d" (hi) + : [event] "r" (event) + ); + + return ((uint64_t) hi << 32) | lo; +} + +void +cachepc_cpuid(void) +{ + asm volatile( + "mov $0x80000005, %%eax\n\t" + "cpuid\n\t" + ::: CPUID_AFFECTED_REGS + ); +} + +void +cachepc_lfence(void) +{ + asm volatile( + "lfence\n\t" + :: + ); +} + +void +cachepc_sfence(void) +{ + asm volatile( + "sfence\n\t" + :: + ); +} + +void +cachepc_mfence(void) +{ + asm volatile( + "mfence\n\t" + :: + ); +} -- cgit v1.2.3-71-gd317