From 2558cb66b59aae1578fc46ff8edf5d7cf9383037 Mon Sep 17 00:00:00 2001 From: Louis Burda Date: Mon, 25 Jul 2022 22:51:20 +0200 Subject: Added proc device for reading counts --- src/cachepc.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/cachepc.h') diff --git a/src/cachepc.h b/src/cachepc.h index c40fc10..72c348b 100755 --- a/src/cachepc.h +++ b/src/cachepc.h @@ -15,7 +15,7 @@ void cachepc_init_counters(void); cache_ctx *cachepc_get_ctx(cache_level cl); cacheline *cachepc_prepare_ds(cache_ctx *ctx); -void cachepc_save_msrmts(cacheline *head, const char *prefix, int index); +void cachepc_save_msrmts(cacheline *head); void cachepc_print_msrmts(cacheline *head); void cachepc_release_ds(cache_ctx *ctx, cacheline *ds); void cachepc_release_ctx(cache_ctx *ctx); @@ -32,6 +32,9 @@ static inline cacheline *cachepc_probe_set(cacheline *curr_cl); __attribute__((always_inline)) static inline cacheline *cachepc_probe(cacheline *head); +extern uint8_t *cachepc_msrmts; +extern size_t cachepc_msrmts_count; + /* * Prime phase: fill the target cache (encoded in the size of the data structure) * with the prepared data structure, i.e. with attacker data. -- cgit v1.2.3-71-gd317