From d8a20a54b05e2c9adb5198b1439608391450dd0b Mon Sep 17 00:00:00 2001 From: Louis Burda Date: Mon, 8 Aug 2022 19:21:29 +0200 Subject: Added ioctl interface and debuged single access evictions --- src/asm.h | 26 +++++++------------- src/cache_types.h | 2 -- src/cachepc.c | 27 ++++++++++++++++++--- src/cachepc.h | 71 +++++++++++++++++------------------------------------- src/cachepc_user.h | 6 +++++ src/util.c | 19 +++++++++++++-- 6 files changed, 77 insertions(+), 74 deletions(-) create mode 100644 src/cachepc_user.h (limited to 'src') diff --git a/src/asm.h b/src/asm.h index 101faa9..35f803b 100755 --- a/src/asm.h +++ b/src/asm.h @@ -22,21 +22,20 @@ static inline void cachepc_mfence(void); __attribute__((always_inline)) static inline void cachepc_readq(void *p); -__attribute__((always_inline)) -static inline void cachepc_victim(void *p); - uint64_t cachepc_readpmc(uint64_t event) { uint32_t lo, hi; + event = 0xC0010201 + 2 * event; + asm volatile ( "rdmsr" : "=a" (lo), "=d" (hi) : "c"(event) ); - return ((uint64_t) hi << 32) | (uint64_t)lo; + return ((uint64_t) hi << 32) | (uint64_t) lo; } void @@ -54,29 +53,29 @@ cachepc_lfence(void) { asm volatile( "lfence\n\t" - :: + ::: "memory" ); } -inline void +void cachepc_sfence(void) { asm volatile( "sfence\n\t" - :: + ::: "memory" ); } -inline void +void cachepc_mfence(void) { asm volatile( "mfence\n\t" - :: + ::: "memory" ); } -inline void +void cachepc_readq(void *p) { asm volatile ( @@ -84,10 +83,3 @@ cachepc_readq(void *p) : : "r" (p) : "r10" ); } - -inline void -cachepc_victim(void *p) -{ - cachepc_mfence(); - cachepc_readq(p); -} diff --git a/src/cache_types.h b/src/cache_types.h index 6bba73d..33da39b 100755 --- a/src/cache_types.h +++ b/src/cache_types.h @@ -2,8 +2,6 @@ #include "device_conf.h" -#include - #define SET_MASK(SETS) (((((uintptr_t) SETS) * CACHELINE_SIZE) - 1) ^ (CACHELINE_SIZE - 1)) #define REMOVE_PAGE_OFFSET(ptr) ((void *) (((uintptr_t) ptr) & PAGE_MASK)) diff --git a/src/cachepc.c b/src/cachepc.c index c7e6048..702cfad 100755 --- a/src/cachepc.c +++ b/src/cachepc.c @@ -1,5 +1,11 @@ #include "cachepc.h" +#include +#include +#include +#include +#include + static void cl_insert(cacheline *last_cl, cacheline *new_cl); static void *remove_cache_set(cache_ctx *ctx, void *ptr); static void *remove_cache_group_set(void *ptr); @@ -26,8 +32,8 @@ cachepc_init_counters(void) */ reg_addr = 0xc0010200; - event_no = 0x64;//0x29;//0x64; - event_mask = 0x08; //0x07; //0x08; + event_no = 0x70; + event_mask = 0xFF; event = event_no | (event_mask << 8); event |= (1ULL << 17); /* OS (kernel) events only */ event |= (1ULL << 22); /* enable performance counter */ @@ -36,14 +42,25 @@ cachepc_init_counters(void) asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); reg_addr = 0xc0010202; - event_no = 0x64; - event_mask = 0xF0; + event_no = 0x71; + event_mask = 0xFF; + event = event_no | (event_mask << 8); + event |= (1ULL << 17); /* OS (kernel) events only */ + event |= (1ULL << 22); /* enable performance counter */ + event |= (1ULL << 40); /* Host events only */ + printk(KERN_WARNING "CachePC: Initialized event %llu\n", event); + asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); + + reg_addr = 0xc0010204; + event_no = 0x72; + event_mask = 0xFF; event = event_no | (event_mask << 8); event |= (1ULL << 17); /* OS (kernel) events only */ event |= (1ULL << 22); /* enable performance counter */ event |= (1ULL << 40); /* Host events only */ printk(KERN_WARNING "CachePC: Initialized event %llu\n", event); asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); + } cache_ctx * @@ -149,6 +166,8 @@ cachepc_save_msrmts(cacheline *head) { cacheline *curr_cl; + printk(KERN_WARNING "CachePC: Updating /proc/cachepc\n"); + curr_cl = head; do { if (IS_FIRST(curr_cl->flags)) { diff --git a/src/cachepc.h b/src/cachepc.h index ccdd2c0..a88edb8 100755 --- a/src/cachepc.h +++ b/src/cachepc.h @@ -1,16 +1,9 @@ #pragma once -#include -#include -#include -#include - #include "asm.h" #include "cache_types.h" #include "util.h" - -#define L2_MISS_CNTR 0xC0010201 -#define L2_HIT_CNTR 0xC0010203 +#include "cachepc_user.h" void cachepc_init_counters(void); @@ -32,12 +25,12 @@ static inline cacheline *cachepc_prime(cacheline *head); __attribute__((always_inline)) static inline cacheline *cachepc_prime_rev(cacheline *head); -//__attribute__((always_inline)) -//static inline cacheline *cachepc_probe_set(cacheline *curr_cl); - __attribute__((always_inline)) static inline cacheline *cachepc_probe(cacheline *head); +__attribute__((always_inline)) +static inline void cachepc_victim(void *p); + extern uint16_t *cachepc_msrmts; extern size_t cachepc_msrmts_count; @@ -101,23 +94,20 @@ cachepc_prime_rev(cacheline *head) cacheline * cachepc_probe(cacheline *start_cl) { - uint64_t pre1, pre2; - uint64_t post1, post2; - volatile int i = 0; + uint64_t pre, post; cacheline *next_cl; cacheline *curr_cl; + volatile register uint64_t i asm("r12"); curr_cl = start_cl; do { - cachepc_cpuid(); + pre = cachepc_readpmc(0); + pre += cachepc_readpmc(1); + cachepc_mfence(); - - pre1 = cachepc_readpmc(L2_HIT_CNTR); - pre2 = cachepc_readpmc(L2_MISS_CNTR); - cachepc_cpuid(); - cachepc_mfence(); + asm volatile( "mov 8(%[curr_cl]), %%rax \n\t" // +8 "mov 8(%%rax), %%rcx \n\t" // +16 @@ -133,45 +123,28 @@ cachepc_probe(cacheline *start_cl) : "rax", "rcx" ); - cachepc_cpuid(); cachepc_mfence(); + cachepc_cpuid(); + post = cachepc_readpmc(0); + post += cachepc_readpmc(1); - cachepc_cpuid(); cachepc_mfence(); - - //msleep(100); - //for(i=0; i<100000; ++i){ - //} - - post1 = cachepc_readpmc(L2_HIT_CNTR); - cachepc_cpuid(); - post2 = cachepc_readpmc(L2_MISS_CNTR); cachepc_cpuid(); /* works across size boundary */ - curr_cl->count = 0; - curr_cl->count += post1 - pre1; - curr_cl->count += post2 - pre2; + curr_cl->count = post - pre; + curr_cl = next_cl; } while (__builtin_expect(curr_cl != start_cl, 1)); return curr_cl->next; } -// static inline cacheline * -// cachepc_probe(cacheline *head) -// { -// cacheline *curr_cs; -// -// //printk(KERN_WARNING "CachePC: Probing.."); -// -// curr_cs = head; -// do { -// curr_cs = cachepc_probe_set(curr_cs); -// } while (__builtin_expect(curr_cs != head, 1)); -// -// //printk(KERN_WARNING "CachePC: Probing done"); -// -// return curr_cs->next; -// } +void +cachepc_victim(void *p) +{ + cachepc_cpuid(); + cachepc_mfence(); + cachepc_readq(p); +} diff --git a/src/cachepc_user.h b/src/cachepc_user.h new file mode 100644 index 0000000..992e2af --- /dev/null +++ b/src/cachepc_user.h @@ -0,0 +1,6 @@ +#pragma once + +#include + +#define CACHEPC_IOCTL_MAGIC 0xBF +#define CACHEPC_IOCTL_ACCESS_TEST _IOR(CACHEPC_IOCTL_MAGIC, 0, int) diff --git a/src/util.c b/src/util.c index 5ad3efa..166ec3e 100755 --- a/src/util.c +++ b/src/util.c @@ -1,6 +1,21 @@ #include "util.h" -#include +static size_t random_pos = 0; +static uint8_t random[] = { 90, 227, 179, 229, 27, 117, 69, 81, 188, 253, 129, 140, 140, 180, 191, 152, 194, 98, 169, 205, 254, 155, 249, 81, 208, 245, 186, 80, 81, 50, 63, 67, 200, 108, 70, 32, 239, 158, 38, 234, 183, 130, 141, 175, 39, 230, 107, 199, 59, 43, 238, 122, 103, 25, 184, 66, 31, 239, 57, 92, 119, 101, 147, 188, 171, 112, 209, 227, 92, 224, 9, 150, 220, 10, 154, 92, 86, 39, 154, 140, 65, 57, 158, 47, 142, 168, 222, 200, 69, 183, 160, 249, 103, 45, 241, 112, 49, 85, 2, 73, 255, 16, 132, 215, 190, 143, 215, 128, 119, 75, 136, 112, 67, 27, 213, 78, 127, 1, 197, 18, 122, 216, 123, 244, 11, 154, 124, 212, 171, 29, 184, 45, 42, 128, 124, 168, 112, 191, 139, 136, 20, 127, 169, 75, 220, 4, 162, 207, 80, 147, 25, 39, 232, 219, 100, 13, 199, 88, 19, 40, 141, 2, 16, 109, 40, 127, 47, 60, 221, 151, 156, 115, 182, 198, 231, 193, 36, 89, 127, 31, 187, 47, 109, 70, 75, 115, 221, 236, 46, 65, 151, 48, 185, 157, 177, 152, 134, 38, 246, 146, 15, 67, 80, 192, 74, 244, 250, 194, 21, 19, 151, 199, 124, 9, 174, 171, 239, 146, 213, 214, 226, 137, 237, 13, 92, 87, 10, 144, 21, 143, 158, 130, 129, 176, 40, 25, 247, 182, 90, 226, 14, 199, 219, 242, 52, 225, 154, 218, 242, 191, 53, 253, 36, 62, 154, 13, 145, 182, 72, 234, 140, 166, 125, 93, 236, 14, 40, 183, 48, 138, 240, 243, 100, 119, 160, 73, 182, 204, 130, 108, 80, 226, 13, 36, 118, 245, 85, 205, 131, 110, 69, 116, 130, 211, 243, 182, 180, 28, 197, 224, 245, 78, 122, 135, 194, 31, 138, 178, 194, 150, 42, 190, 7, 217, 100, 19, 161, 154, 237, 76, 135, 63, 2, 33, 229, 164, 223, 175, 0, 51, 177, 78, 13, 241, 198, 152, 109, 166, 92, 226, 42, 213, 148, 149, 144, 39, 20, 51, 239, 153, 56, 198, 190, 165, 243, 108, 66, 132, 127, 179, 182, 211, 207, 107, 223, 188, 198, 103, 147, 127, 87, 187, 137, 123, 72, 141, 156, 28, 76, 234, 244, 108, 176, 227, 221, 26, 110, 81, 28, 187, 14, 24, 82, 218, 201, 156, 20, 184, 105, 117, 188, 132, 243, 11, 13, 188, 243, 181, 98, 136, 124, 152, 254, 228, 221, 114, 140, 103, 44, 55, 147, 227, 241, 96, 198, 27, 98, 35, 179, 6, 244, 17, 152, 128, 44, 75, 8, 18, 122, 79, 244, 210, 8, 168, 99, 80, 19, 100, 38, 6, 243, 216, 200, 105, 164, 29, 171, 232, 247, 218, 17, 133, 232, 68, 140, 100, 106, 49, 17, 90, 178, 38, 69, 238, 23, 174, 180, 90, 18, 12, 71, 45, 101, 200, 83, 77, 95, 218, 91, 176, 63, 179, 203, 125, 56, 171, 218, 98, 135, 127, 214, 63, 41, 151, 197, 157, 192, 152, 67, 67, 157, 54, 123, 111, 118, 45, 94, 15, 81, 123, 125, 169, 67, 50, 150, 113, 147, 13, 16, 86, 2, 135, 129, 88, 154, 246, 170, 223, 47, 247, 190, 187, 35, 213, 194, 67, 226, 181, 208, 135, 75, 30, 233, 136, 45, 222, 121, 60, 157, 48, 171, 244, 52, 40, 187, 8, 23, 173, 41, 157, 165, 158, 92, 139, 22, 95, 72, 164, 142, 213, 156, 102, 196, 108, 228, 203, 99, 72, 254, 173, 37, 212, 150, 145, 104, 76, 117, 242, 185, 180, 108, 50, 188, 206, 40, 52, 55, 147, 240, 89, 248, 203, 110, 237, 24, 88, 63, 99, 224, 121, 229, 90, 253, 12, 72, 24, 3, 247, 127, 35, 178, 198, 80, 151, 223, 243, 195, 114, 5, 134, 250, 85, 182, 154, 206, 41, 53, 50, 59, 174, 117, 203, 200, 33, 182, 230, 147, 101, 36, 111, 23, 187, 130, 16, 211, 90, 102, 207, 154, 140, 123, 212, 66, 45, 35, 165, 139, 109, 169, 226, 210, 115, 16, 92, 196, 31, 245, 154, 110, 181, 161, 126, 184, 177, 237, 125, 181, 71, 120, 86, 222, 179, 133, 113, 72, 206, 157, 89, 162, 80, 164, 223, 38, 17, 238, 114, 188, 125, 69, 1, 28, 126, 249, 180, 189, 144, 215, 152, 89, 92, 62, 98, 151, 242, 46, 48, 162, 3, 95, 211, 122, 217, 36, 235, 109, 100, 94, 233, 173, 150, 71, 125, 201, 168, 4, 180, 248, 249, 240, 50, 206, 242, 169, 201, 31, 137, 198, 93, 241, 219, 11, 9, 1, 229, 249, 194, 67, 41, 143, 117, 103, 238, 247, 72, 178, 21, 193, 146, 119, 159, 21, 253, 206, 66, 186, 60, 200, 102, 179, 117, 103, 32, 0, 116, 31, 133, 129, 127, 38, 5, 177, 195, 25, 23, 86, 29, 222, 53, 0, 140, 179, 118, 239, 141, 237, 122, 80, 200, 92, 47, 15, 58, 167, 26, 37, 146, 254, 3, 74, 148, 159, 221, 38, 68, 110, 98, 82, 16, 171, 232, 139, 72, 87, 114, 113, 61, 210, 82, 180, 196, 8, 14, 249, 185, 159, 253, 166, 200, 82, 176, 112, 173, 246, 40, 22, 202, 140, 76, 60, 92, 225, 10, 198, 41, 26, 223, 250, 181, 135, 196, 230, 10, 103, 197, 128, 155, 148, 121, 150, 51, 196, 143, 183, 153, 229, 93, 118, 12, 235, 237, 105, 73, 27, 24, 86, 248, 39, 190, 71, 184, 212, 74, 196, 181, 46, 140, 9, 18, 168, 110, 30, 93, 166, 44, 153, 88, 82, 148, 237, 146, 173, 158, 29, 215, 202, 3, 224, 240, 186, 202, 52, 123, 244, 226, 109, 79, 174, 245, 35, 242, 82, 187, 101, 69, 245, 104, 139, 118, 134, 236, 135, 243, 10, 149, 162, 212, 245, 132, 3, 90, 38, 96, 28, 98, 200, 80, 141, 252, 40, 214, 80, 152, 221, 239, 166, 135, 104, 105, 227, 248, 102, 53, 78, 186, 95, 15, 97, 58, 129, 98, 219, 233, 167, 89, 198, 175, 98, 77, 20, 182, 112, 104, 165, 34 }; + +void +prng_bytes(uint8_t *dst, size_t size) +{ + size_t i; + + if (random_pos + size > sizeof(random)) + random_pos = 0; + + for (i = 0; i < size; i++) + dst[i] = random[random_pos + i]; + + random_pos += size; +} void random_perm(uint32_t *arr, uint32_t arr_len) @@ -8,7 +23,7 @@ random_perm(uint32_t *arr, uint32_t arr_len) uint32_t i, idx, tmp; for (i = arr_len - 1; i > 0; --i) { - get_random_bytes(&idx, 4); + prng_bytes((void*)&idx, 4); idx = idx % i; tmp = arr[idx]; -- cgit v1.2.3-71-gd317