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* Update Makefile to compile raylib ourselvesHEADmasterLouis Burda2023-08-163-10/+15
* Merge branch 'master' of sinitax.com:sinitax/chall-tis256Louis Burda2023-08-161-0/+0
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| * Only set select() timeout when necessary to avoid flickeringLouis Burda2023-08-162-11/+15
* | Only set select() timeout when necessary to avoid flickeringLouis Burda2023-08-131-11/+15
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* Fix release MakefileLouis Burda2023-08-134-9/+50
* Delimit flag by newline, prevent char-by-char bruteforceLouis Burda2023-08-104-258/+295
* Fix flag format to ALLES!{...}Louis Burda2023-08-102-227/+228
* Add decode script to verify solutionLouis Burda2023-08-101-0/+19
* Remove misleading dec instruction from decoderLouis Burda2023-08-104-1907/+1899
* Make README more clear, add seed to transform for determinismLouis Burda2023-08-1018-6/+19036
* Update tis256, reorganize release and remove unconnected tpu in cpu.asmLouis Burda2023-08-1018-19032/+12
* Update tis256Louis Burda2023-08-098-21/+87
* Add basic readme and improve buildLouis Burda2023-08-0913-9723/+2721
* Refactor repo to separate release files and pin tis256 commitLouis Burda2023-08-0862-78/+26106
* Rewrite for jeq/jne, new main memory type, drawing & transformLouis Burda2023-08-0512-490/+339
* Use shl/shr in decoderLouis Burda2023-08-041-47/+8
* Split memory into banks, compress bus more, final asm worksLouis Burda2023-08-0427-26005/+422
* Tighten up bus using collision checkLouis Burda2023-08-041-40/+62
* Implement rotated parts on busLouis Burda2023-08-047-489/+299
* Implement rest of instructions and test some -- perf is lackingLouis Burda2023-08-0434-9260/+22542
* Implement more instructionsLouis Burda2023-08-0316-150/+1030
* Add script to add devices to central communications busLouis Burda2023-08-0313-62/+419
* Prelim ideas / cpu partsLouis Burda2023-08-015-147/+14037
* Stash outlineLouis Burda2023-07-251-0/+147
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