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| author | Thierry Reding <treding@nvidia.com> | 2020-07-21 17:10:55 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-08-27 17:37:37 +0200 |
| commit | 818ae79a50da560c645e022170bed8401eea452e (patch) | |
| tree | f8d9e2191e84de13bad56a256562baa83a45ad3d | |
| parent | 562da8b494c4e2f72d0789a03e6ccd9dc14d3f25 (diff) | |
| download | cachepc-linux-818ae79a50da560c645e022170bed8401eea452e.tar.gz cachepc-linux-818ae79a50da560c645e022170bed8401eea452e.zip | |
arm64: tegra: Properly size register regions for GPU on Tegra194
Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
than 256 MiB.
Reported-by: Terje Bergström <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-By: Terje Bergström <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 466872a4512f..421b9e0883d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1412,8 +1412,8 @@ gpu@17000000 { compatible = "nvidia,gv11b"; - reg = <0x17000000 0x10000000>, - <0x18000000 0x10000000>; + reg = <0x17000000 0x1000000>, + <0x18000000 0x1000000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "stall", "nonstall"; |