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authorChen-Yu Tsai <wens@csie.org>2017-05-22 14:25:51 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-05-22 09:22:33 +0200
commit9ecf12302cd2baaba2dfedc0173978ab37416866 (patch)
tree0894927db34bd0463c3629a36c75be0725bd652e
parent749b7a9775a63bc8b87bbbe185d849df4c39158d (diff)
downloadcachepc-linux-9ecf12302cd2baaba2dfedc0173978ab37416866.tar.gz
cachepc-linux-9ecf12302cd2baaba2dfedc0173978ab37416866.zip
ARM: sun8i: a83t: Add device node for SPDIF transmitter
The A83T SoC has an SPDIF transmitter block. According to the vendor BSP kernel, it is compatible with the one found on the H3 SoC. Add a device node and pinmux setting for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 47196feda26b..1dc4cfe81534 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -202,6 +202,11 @@
bias-pull-up;
};
+ spdif_tx_pin: spdif-tx-pin {
+ pins = "PE18";
+ function = "spdif";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
@@ -228,6 +233,22 @@
clocks = <&osc24M>;
};
+ spdif: spdif@1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-spdif",
+ "allwinner,sun8i-h3-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 44>, <&ccu 76>;
+ resets = <&ccu 32>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ status = "disabled";
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;