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| author | Christian Vogel <vogelchr@vogel.cx> | 2021-01-13 20:50:17 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-01-20 18:50:21 +0100 |
| commit | 48b7de6687f6ed597ef7162151f1c35469775545 (patch) | |
| tree | 8b7bf12fdf71e44c3c17e788cb1c7409fc3be04b /include/linux/debugobjects.h | |
| parent | 20612d2428c3cdd191d45d548e930f41785f62cc (diff) | |
| download | cachepc-linux-48b7de6687f6ed597ef7162151f1c35469775545.tar.gz cachepc-linux-48b7de6687f6ed597ef7162151f1c35469775545.zip | |
w1/w1.c: w1 address crc quick for DS28E04 eeproms
Onewire addresses are 64bit family(8bit), unique_id(48bit), crc(8bit)
(LSBt to MSB) and self-consistent: crc = crc8(family, unique).
DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO have strap pins
to set 7 LSB of the address, unfortunately without updating the crc
part of the address. It is only consistent if all strap pins float high.
[see datasheet 19-6134; Rev 12/11 page 6: 64-bit device id number]
We therefore introduce a special handling of family 0x1c (DS28E04) to
check address consistency with 7 LSBs of the unique_id set to 1.
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
Signed-off-by: Christian Vogel <vogelchr@vogel.cx>
Link: https://lore.kernel.org/r/20210113195018.7498-2-vogelchr@vogel.cx
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/debugobjects.h')
0 files changed, 0 insertions, 0 deletions