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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-06-29 07:35:30 -0500 |
|---|---|---|
| committer | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-07-13 17:27:23 -0500 |
| commit | d93ac9547792156b871c050495fef8780286311f (patch) | |
| tree | de80d0019e65c230fef67dffdf3ad4c383547de2 /include/linux/debugobjects.h | |
| parent | 36ac6c50deaafcdcdecc7a68723400beb734b1e3 (diff) | |
| download | cachepc-linux-d93ac9547792156b871c050495fef8780286311f.tar.gz cachepc-linux-d93ac9547792156b871c050495fef8780286311f.zip | |
iommu/amd: Introduce Support for Extended Feature 2 Register
AMD IOMMU spec introduces additional extended feature register
in the IVRS IVHD offset 80h (for IVHD type 11h and 40h) and MMIO
offset 1A0h.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Diffstat (limited to 'include/linux/debugobjects.h')
0 files changed, 0 insertions, 0 deletions