diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2022-01-15 12:09:44 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2022-01-15 12:09:44 -0800 |
| commit | 762f99f4f3cb41a775b5157dd761217beba65873 (patch) | |
| tree | 2e93410a577dfff1202ea5b0d109460b97650e58 /include/linux/mfd | |
| parent | cf73ed894ee939d6706d65e0cd186e4a64e3af6d (diff) | |
| parent | b6e43dddaea3dbfa93327f986beb3ec5e8157c4c (diff) | |
| download | cachepc-linux-762f99f4f3cb41a775b5157dd761217beba65873.tar.gz cachepc-linux-762f99f4f3cb41a775b5157dd761217beba65873.zip | |
Merge branch 'next' into for-linus
Prepare input updates for 5.17 merge window.
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/dbx500-prcmu.h | 3 | ||||
| -rw-r--r-- | include/linux/mfd/hi6421-spmi-pmic.h | 5 | ||||
| -rw-r--r-- | include/linux/mfd/hi655x-pmic.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/idt82p33_reg.h | 112 | ||||
| -rw-r--r-- | include/linux/mfd/idt8a340_reg.h | 729 | ||||
| -rw-r--r-- | include/linux/mfd/lp87565.h | 40 | ||||
| -rw-r--r-- | include/linux/mfd/madera/pdata.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/mt6358/core.h | 8 | ||||
| -rw-r--r-- | include/linux/mfd/mt6358/registers.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/mt6359/core.h | 133 | ||||
| -rw-r--r-- | include/linux/mfd/mt6359/registers.h | 529 | ||||
| -rw-r--r-- | include/linux/mfd/mt6359p/registers.h | 249 | ||||
| -rw-r--r-- | include/linux/mfd/mt6360.h | 240 | ||||
| -rw-r--r-- | include/linux/mfd/mt6397/core.h | 1 | ||||
| -rw-r--r-- | include/linux/mfd/mt6397/rtc.h | 1 | ||||
| -rw-r--r-- | include/linux/mfd/rk808.h | 81 | ||||
| -rw-r--r-- | include/linux/mfd/rsmu.h | 36 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/core.h | 33 | ||||
| -rw-r--r-- | include/linux/mfd/wcd934x/registers.h | 57 |
19 files changed, 1952 insertions, 311 deletions
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index e6ee2ec35de9..cbf9d7619493 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -186,10 +186,11 @@ enum ddr_pwrst { #define PRCMU_FW_PROJECT_U8500_C3 8 #define PRCMU_FW_PROJECT_U8500_C4 9 #define PRCMU_FW_PROJECT_U9500_MBL 10 -#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ +#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */ #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ #define PRCMU_FW_PROJECT_U8520 13 #define PRCMU_FW_PROJECT_U8420 14 +#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */ #define PRCMU_FW_PROJECT_U8420_SYSCLK 17 #define PRCMU_FW_PROJECT_A9420 20 /* [32..63] 9540 and derivatives */ diff --git a/include/linux/mfd/hi6421-spmi-pmic.h b/include/linux/mfd/hi6421-spmi-pmic.h index 2660226138b8..e5b8dbf828b6 100644 --- a/include/linux/mfd/hi6421-spmi-pmic.h +++ b/include/linux/mfd/hi6421-spmi-pmic.h @@ -19,11 +19,6 @@ struct hi6421_spmi_pmic { struct resource *res; struct device *dev; void __iomem *regs; - spinlock_t lock; - struct irq_domain *domain; - int irq; - int gpio; - unsigned int *irqs; struct regmap *regmap; }; diff --git a/include/linux/mfd/hi655x-pmic.h b/include/linux/mfd/hi655x-pmic.h index b06171322178..af5d97239c0d 100644 --- a/include/linux/mfd/hi655x-pmic.h +++ b/include/linux/mfd/hi655x-pmic.h @@ -2,7 +2,7 @@ /* * Device driver for regulators in hi655x IC * - * Copyright (c) 2016 Hisilicon. + * Copyright (c) 2016 HiSilicon Ltd. * * Authors: * Chen Feng <puck.chen@hisilicon.com> diff --git a/include/linux/mfd/idt82p33_reg.h b/include/linux/mfd/idt82p33_reg.h new file mode 100644 index 000000000000..129a6c078221 --- /dev/null +++ b/include/linux/mfd/idt82p33_reg.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ +#ifndef HAVE_IDT82P33_REG +#define HAVE_IDT82P33_REG + +/* Register address */ +#define DPLL1_TOD_CNFG 0x134 +#define DPLL2_TOD_CNFG 0x1B4 + +#define DPLL1_TOD_STS 0x10B +#define DPLL2_TOD_STS 0x18B + +#define DPLL1_TOD_TRIGGER 0x115 +#define DPLL2_TOD_TRIGGER 0x195 + +#define DPLL1_OPERATING_MODE_CNFG 0x120 +#define DPLL2_OPERATING_MODE_CNFG 0x1A0 + +#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C +#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC + +#define DPLL1_PHASE_OFFSET_CNFG 0x143 +#define DPLL2_PHASE_OFFSET_CNFG 0x1C3 + +#define DPLL1_SYNC_EDGE_CNFG 0x140 +#define DPLL2_SYNC_EDGE_CNFG 0x1C0 + +#define DPLL1_INPUT_MODE_CNFG 0x116 +#define DPLL2_INPUT_MODE_CNFG 0x196 + +#define DPLL1_OPERATING_STS 0x102 +#define DPLL2_OPERATING_STS 0x182 + +#define DPLL1_CURRENT_FREQ_STS 0x103 +#define DPLL2_CURRENT_FREQ_STS 0x183 + +#define REG_SOFT_RESET 0X381 + +#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn))) + +/* Register bit definitions */ +#define SYNC_TOD BIT(1) +#define PH_OFFSET_EN BIT(7) +#define SQUELCH_ENABLE BIT(5) + +/* Bit definitions for the DPLL_MODE register */ +#define PLL_MODE_SHIFT (0) +#define PLL_MODE_MASK (0x1F) +#define COMBO_MODE_EN BIT(5) +#define COMBO_MODE_SHIFT (6) +#define COMBO_MODE_MASK (0x3) + +/* Bit definitions for DPLL_OPERATING_STS register */ +#define OPERATING_STS_MASK (0x7) +#define OPERATING_STS_SHIFT (0x0) + +/* Bit definitions for DPLL_TOD_TRIGGER register */ +#define READ_TRIGGER_MASK (0xF) +#define READ_TRIGGER_SHIFT (0x0) +#define WRITE_TRIGGER_MASK (0xF0) +#define WRITE_TRIGGER_SHIFT (0x4) + +/* Bit definitions for REG_SOFT_RESET register */ +#define SOFT_RESET_EN BIT(7) + +enum pll_mode { + PLL_MODE_MIN = 0, + PLL_MODE_AUTOMATIC = PLL_MODE_MIN, + PLL_MODE_FORCE_FREERUN = 1, + PLL_MODE_FORCE_HOLDOVER = 2, + PLL_MODE_FORCE_LOCKED = 4, + PLL_MODE_FORCE_PRE_LOCKED2 = 5, + PLL_MODE_FORCE_PRE_LOCKED = 6, + PLL_MODE_FORCE_LOST_PHASE = 7, + PLL_MODE_DCO = 10, + PLL_MODE_WPH = 18, + PLL_MODE_MAX = PLL_MODE_WPH, +}; + +enum hw_tod_trig_sel { + HW_TOD_TRIG_SEL_MIN = 0, + HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN, + HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN, + HW_TOD_TRIG_SEL_SYNC_SEL = 1, + HW_TOD_TRIG_SEL_IN12 = 2, + HW_TOD_TRIG_SEL_IN13 = 3, + HW_TOD_TRIG_SEL_IN14 = 4, + HW_TOD_TRIG_SEL_TOD_PPS = 5, + HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6, + HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7, + HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8, + HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9, + HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, + WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, +}; + +/** @brief Enumerated type listing DPLL operational modes */ +enum dpll_state { + DPLL_STATE_FREERUN = 1, + DPLL_STATE_HOLDOVER = 2, + DPLL_STATE_LOCKED = 4, + DPLL_STATE_PRELOCKED2 = 5, + DPLL_STATE_PRELOCKED = 6, + DPLL_STATE_LOSTPHASE = 7, + DPLL_STATE_MAX +}; + +#endif diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h new file mode 100644 index 000000000000..92d763230bdf --- /dev/null +++ b/include/linux/mfd/idt8a340_reg.h @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on 5.2.0, Family Programming Guide (Sept 30, 2020) + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ +#ifndef HAVE_IDT8A340_REG +#define HAVE_IDT8A340_REG + +#define PAGE_ADDR_BASE 0x0000 +#define PAGE_ADDR 0x00fc + +#define HW_REVISION 0x8180 +#define REV_ID 0x007a + +#define HW_DPLL_0 (0x8a00) +#define HW_DPLL_1 (0x8b00) +#define HW_DPLL_2 (0x8c00) +#define HW_DPLL_3 (0x8d00) +#define HW_DPLL_4 (0x8e00) +#define HW_DPLL_5 (0x8f00) +#define HW_DPLL_6 (0x9000) +#define HW_DPLL_7 (0x9100) + +#define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080) +#define HW_DPLL_TOD_CTRL_1 (0x089) +#define HW_DPLL_TOD_CTRL_2 (0x08A) +#define HW_DPLL_TOD_OVR__0 (0x098) +#define HW_DPLL_TOD_OUT_0__0 (0x0B0) + +#define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740) +#define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741) +#define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742) +#define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743) +#define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744) +#define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745) +#define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746) +#define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747) +#define HW_Q8_CH_SYNC_CTRL_0 (0xa748) +#define HW_Q8_CH_SYNC_CTRL_1 (0xa749) +#define HW_Q9_CH_SYNC_CTRL_0 (0xa74a) +#define HW_Q9_CH_SYNC_CTRL_1 (0xa74b) +#define HW_Q10_CH_SYNC_CTRL_0 (0xa74c) +#define HW_Q10_CH_SYNC_CTRL_1 (0xa74d) +#define HW_Q11_CH_SYNC_CTRL_0 (0xa74e) +#define HW_Q11_CH_SYNC_CTRL_1 (0xa74f) + +#define SYNC_SOURCE_DPLL0_TOD_PPS 0x14 +#define SYNC_SOURCE_DPLL1_TOD_PPS 0x15 +#define SYNC_SOURCE_DPLL2_TOD_PPS 0x16 +#define SYNC_SOURCE_DPLL3_TOD_PPS 0x17 + +#define SYNCTRL1_MASTER_SYNC_RST BIT(7) +#define SYNCTRL1_MASTER_SYNC_TRIG BIT(5) +#define SYNCTRL1_TOD_SYNC_TRIG BIT(4) +#define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3) +#define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2) +#define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1) +#define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0) + +#define HW_Q8_CTRL_SPARE (0xa7d4) +#define HW_Q11_CTRL_SPARE (0xa7ec) + +/** + * Select FOD5 as sync_trigger for Q8 divider. + * Transition from logic zero to one + * sets trigger to sync Q8 divider. + * + * Unused when FOD4 is driving Q8 divider (normal operation). + */ +#define Q9_TO_Q8_SYNC_TRIG BIT(1) + +/** + * Enable FOD5 as driver for clock and sync for Q8 divider. + * Enable fanout buffer for FOD5. + * + * Unused when FOD4 is driving Q8 divider (normal operation). + */ +#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) + +/** + * Select FOD6 as sync_trigger for Q11 divider. + * Transition from logic zero to one + * sets trigger to sync Q11 divider. + * + * Unused when FOD7 is driving Q11 divider (normal operation). + */ +#define Q10_TO_Q11_SYNC_TRIG BIT(1) + +/** + * Enable FOD6 as driver for clock and sync for Q11 divider. + * Enable fanout buffer for FOD6. + * + * Unused when FOD7 is driving Q11 divider (normal operation). + */ +#define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) + +#define RESET_CTRL 0xc000 +#define SM_RESET 0x0012 +#define SM_RESET_V520 0x0013 +#define SM_RESET_CMD 0x5A + +#define GENERAL_STATUS 0xc014 +#define BOOT_STATUS 0x0000 +#define HW_REV_ID 0x000A +#define BOND_ID 0x000B +#define HW_CSR_ID 0x000C +#define HW_IRQ_ID 0x000E +#define MAJ_REL 0x0010 +#define MIN_REL 0x0011 +#define HOTFIX_REL 0x0012 +#define PIPELINE_ID 0x0014 +#define BUILD_ID 0x0018 +#define JTAG_DEVICE_ID 0x001c +#define PRODUCT_ID 0x001e +#define OTP_SCSR_CONFIG_SELECT 0x0022 + +#define STATUS 0xc03c +#define DPLL0_STATUS 0x0018 +#define DPLL1_STATUS 0x0019 +#define DPLL2_STATUS 0x001a +#define DPLL3_STATUS 0x001b +#define DPLL4_STATUS 0x001c +#define DPLL5_STATUS 0x001d +#define DPLL6_STATUS 0x001e +#define DPLL7_STATUS 0x001f +#define DPLL_SYS_STATUS 0x0020 +#define DPLL_SYS_APLL_STATUS 0x0021 +#define DPLL0_FILTER_STATUS 0x0044 +#define DPLL1_FILTER_STATUS 0x004c +#define DPLL2_FILTER_STATUS 0x0054 +#define DPLL3_FILTER_STATUS 0x005c +#define DPLL4_FILTER_STATUS 0x0064 +#define DPLL5_FILTER_STATUS 0x006c +#define DPLL6_FILTER_STATUS 0x0074 +#define DPLL7_FILTER_STATUS 0x007c +#define DPLLSYS_FILTER_STATUS 0x0084 +#define USER_GPIO0_TO_7_STATUS 0x008a +#define USER_GPIO8_TO_15_STATUS 0x008b + +#define GPIO_USER_CONTROL 0xc160 +#define GPIO0_TO_7_OUT 0x0000 +#define GPIO8_TO_15_OUT 0x0001 +#define GPIO0_TO_7_OUT_V520 0x0002 +#define GPIO8_TO_15_OUT_V520 0x0003 + +#define STICKY_STATUS_CLEAR 0xc164 + +#define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c + +#define ALERT_CFG 0xc188 + +#define SYS_DPLL_XO 0xc194 + +#define SYS_APLL 0xc19c + +#define INPUT_0 0xc1b0 +#define INPUT_1 0xc1c0 +#define INPUT_2 0xc1d0 +#define INPUT_3 0xc200 +#define INPUT_4 0xc210 +#define INPUT_5 0xc220 +#define INPUT_6 0xc230 +#define INPUT_7 0xc240 +#define INPUT_8 0xc250 +#define INPUT_9 0xc260 +#define INPUT_10 0xc280 +#define INPUT_11 0xc290 +#define INPUT_12 0xc2a0 +#define INPUT_13 0xc2b0 +#define INPUT_14 0xc2c0 +#define INPUT_15 0xc2d0 + +#define REF_MON_0 0xc2e0 +#define REF_MON_1 0xc2ec +#define REF_MON_2 0xc300 +#define REF_MON_3 0xc30c +#define REF_MON_4 0xc318 +#define REF_MON_5 0xc324 +#define REF_MON_6 0xc330 +#define REF_MON_7 0xc33c +#define REF_MON_8 0xc348 +#define REF_MON_9 0xc354 +#define REF_MON_10 0xc360 +#define REF_MON_11 0xc36c +#define REF_MON_12 0xc380 +#define REF_MON_13 0xc38c +#define REF_MON_14 0xc398 +#define REF_MON_15 0xc3a4 + +#define DPLL_0 0xc3b0 +#define DPLL_CTRL_REG_0 0x0002 +#define DPLL_CTRL_REG_1 0x0003 +#define DPLL_CTRL_REG_2 0x0004 +#define DPLL_TOD_SYNC_CFG 0x0031 +#define DPLL_COMBO_SLAVE_CFG_0 0x0032 +#define DPLL_COMBO_SLAVE_CFG_1 0x0033 +#define DPLL_SLAVE_REF_CFG 0x0034 +#define DPLL_REF_MODE 0x0035 +#define DPLL_PHASE_MEASUREMENT_CFG 0x0036 +#define DPLL_MODE 0x0037 +#define DPLL_MODE_V520 0x003B +#define DPLL_1 0xc400 +#define DPLL_2 0xc438 +#define DPLL_2_V520 0xc43c +#define DPLL_3 0xc480 +#define DPLL_4 0xc4b8 +#define DPLL_4_V520 0xc4bc +#define DPLL_5 0xc500 +#define DPLL_6 0xc538 +#define DPLL_6_V520 0xc53c +#define DPLL_7 0xc580 +#define SYS_DPLL 0xc5b8 +#define SYS_DPLL_V520 0xc5bc + +#define DPLL_CTRL_0 0xc600 +#define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001 +#define DPLL_CTRL_DPLL_FOD_FREQ 0x001c +#define DPLL_CTRL_COMBO_MASTER_CFG 0x003a +#define DPLL_CTRL_1 0xc63c +#define DPLL_CTRL_2 0xc680 +#define DPLL_CTRL_3 0xc6bc +#define DPLL_CTRL_4 0xc700 +#define DPLL_CTRL_5 0xc73c +#define DPLL_CTRL_6 0xc780 +#define DPLL_CTRL_7 0xc7bc +#define SYS_DPLL_CTRL 0xc800 + +#define DPLL_PHASE_0 0xc818 +/* Signed 42-bit FFO in units of 2^(-53) */ +#define DPLL_WR_PHASE 0x0000 +#define DPLL_PHASE_1 0xc81c +#define DPLL_PHASE_2 0xc820 +#define DPLL_PHASE_3 0xc824 +#define DPLL_PHASE_4 0xc828 +#define DPLL_PHASE_5 0xc82c +#define DPLL_PHASE_6 0xc830 +#define DPLL_PHASE_7 0xc834 + +#define DPLL_FREQ_0 0xc838 +/* Signed 42-bit FFO in units of 2^(-53) */ +#define DPLL_WR_FREQ 0x0000 +#define DPLL_FREQ_1 0xc840 +#define DPLL_FREQ_2 0xc848 +#define DPLL_FREQ_3 0xc850 +#define DPLL_FREQ_4 0xc858 +#define DPLL_FREQ_5 0xc860 +#define DPLL_FREQ_6 0xc868 +#define DPLL_FREQ_7 0xc870 + +#define DPLL_PHASE_PULL_IN_0 0xc880 +#define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */ +#define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */ +#define PULL_IN_CTRL 0x0007 +#define DPLL_PHASE_PULL_IN_1 0xc888 +#define DPLL_PHASE_PULL_IN_2 0xc890 +#define DPLL_PHASE_PULL_IN_3 0xc898 +#define DPLL_PHASE_PULL_IN_4 0xc8a0 +#define DPLL_PHASE_PULL_IN_5 0xc8a8 +#define DPLL_PHASE_PULL_IN_6 0xc8b0 +#define DPLL_PHASE_PULL_IN_7 0xc8b8 + +#define GPIO_CFG 0xc8c0 +#define GPIO_CFG_GBL 0x0000 +#define GPIO_0 0xc8c2 +#define GPIO_DCO_INC_DEC 0x0000 +#define GPIO_OUT_CTRL_0 0x0001 +#define GPIO_OUT_CTRL_1 0x0002 +#define GPIO_TOD_TRIG 0x0003 +#define GPIO_DPLL_INDICATOR 0x0004 +#define GPIO_LOS_INDICATOR 0x0005 +#define GPIO_REF_INPUT_DSQ_0 0x0006 +#define GPIO_REF_INPUT_DSQ_1 0x0007 +#define GPIO_REF_INPUT_DSQ_2 0x0008 +#define GPIO_REF_INPUT_DSQ_3 0x0009 +#define GPIO_MAN_CLK_SEL_0 0x000a +#define GPIO_MAN_CLK_SEL_1 0x000b +#define GPIO_MAN_CLK_SEL_2 0x000c +#define GPIO_SLAVE 0x000d +#define GPIO_ALERT_OUT_CFG 0x000e +#define GPIO_TOD_NOTIFICATION_CFG 0x000f +#define GPIO_CTRL 0x0010 +#define GPIO_CTRL_V520 0x0011 +#define GPIO_1 0xc8d4 +#define GPIO_2 0xc8e6 +#define GPIO_3 0xc900 +#define GPIO_4 0xc912 +#define GPIO_5 0xc924 +#define GPIO_6 0xc936 +#define GPIO_7 0xc948 +#define GPIO_8 0xc95a +#define GPIO_9 0xc980 +#define GPIO_10 0xc992 +#define GPIO_11 0xc9a4 +#define GPIO_12 0xc9b6 +#define GPIO_13 0xc9c8 +#define GPIO_14 0xc9da +#define GPIO_15 0xca00 + +#define OUT_DIV_MUX 0xca12 +#define OUTPUT_0 0xca14 +#define OUTPUT_0_V520 0xca20 +/* FOD frequency output divider value */ +#define OUT_DIV 0x0000 +#define OUT_DUTY_CYCLE_HIGH 0x0004 +#define OUT_CTRL_0 0x0008 +#define OUT_CTRL_1 0x0009 +/* Phase adjustment in FOD cycles */ +#define OUT_PHASE_ADJ 0x000c +#define OUTPUT_1 0xca24 +#define OUTPUT_1_V520 0xca30 +#define OUTPUT_2 0xca34 +#define OUTPUT_2_V520 0xca40 +#define OUTPUT_3 0xca44 +#define OUTPUT_3_V520 0xca50 +#define OUTPUT_4 0xca54 +#define OUTPUT_4_V520 0xca60 +#define OUTPUT_5 0xca64 +#define OUTPUT_5_V520 0xca80 +#define OUTPUT_6 0xca80 +#define OUTPUT_6_V520 0xca90 +#define OUTPUT_7 0xca90 +#define OUTPUT_7_V520 0xcaa0 +#define OUTPUT_8 0xcaa0 +#define OUTPUT_8_V520 0xcab0 +#define OUTPUT_9 0xcab0 +#define OUTPUT_9_V520 0xcac0 +#define OUTPUT_10 0xcac0 +#define OUTPUT_10_V520 0xcad0 +#define OUTPUT_11 0xcad0 +#define OUTPUT_11_V520 0xcae0 + +#define SERIAL 0xcae0 +#define SERIAL_V520 0xcaf0 + +#define PWM_ENCODER_0 0xcb00 +#define PWM_ENCODER_1 0xcb08 +#define PWM_ENCODER_2 0xcb10 +#define PWM_ENCODER_3 0xcb18 +#define PWM_ENCODER_4 0xcb20 +#define PWM_ENCODER_5 0xcb28 +#define PWM_ENCODER_6 0xcb30 +#define PWM_ENCODER_7 0xcb38 +#define PWM_DECODER_0 0xcb40 +#define PWM_DECODER_1 0xcb48 +#define PWM_DECODER_1_V520 0xcb4a +#define PWM_DECODER_2 0xcb50 +#define PWM_DECODER_2_V520 0xcb54 +#define PWM_DECODER_3 0xcb58 +#define PWM_DECODER_3_V520 0xcb5e +#define PWM_DECODER_4 0xcb60 +#define PWM_DECODER_4_V520 0xcb68 +#define PWM_DECODER_5 0xcb68 +#define PWM_DECODER_5_V520 0xcb80 +#define PWM_DECODER_6 0xcb70 +#define PWM_DECODER_6_V520 0xcb8a +#define PWM_DECODER_7 0xcb80 +#define PWM_DECODER_7_V520 0xcb94 +#define PWM_DECODER_8 0xcb88 +#define PWM_DECODER_8_V520 0xcb9e +#define PWM_DECODER_9 0xcb90 +#define PWM_DECODER_9_V520 0xcba8 +#define PWM_DECODER_10 0xcb98 +#define PWM_DECODER_10_V520 0xcbb2 +#define PWM_DECODER_11 0xcba0 +#define PWM_DECODER_11_V520 0xcbbc +#define PWM_DECODER_12 0xcba8 +#define PWM_DECODER_12_V520 0xcbc6 +#define PWM_DECODER_13 0xcbb0 +#define PWM_DECODER_13_V520 0xcbd0 +#define PWM_DECODER_14 0xcbb8 +#define PWM_DECODER_14_V520 0xcbda +#define PWM_DECODER_15 0xcbc0 +#define PWM_DECODER_15_V520 0xcbe4 +#define PWM_USER_DATA 0xcbc8 +#define PWM_USER_DATA_V520 0xcbf0 + +#define TOD_0 0xcbcc +#define TOD_0_V520 0xcc00 +/* Enable TOD counter, output channel sync and even-PPS mode */ +#define TOD_CFG 0x0000 +#define TOD_CFG_V520 0x0001 +#define TOD_1 0xcbce +#define TOD_1_V520 0xcc02 +#define TOD_2 0xcbd0 +#define TOD_2_V520 0xcc04 +#define TOD_3 0xcbd2 +#define TOD_3_V520 0xcc06 + +#define TOD_WRITE_0 0xcc00 +#define TOD_WRITE_0_V520 0xcc10 +/* 8-bit subns, 32-bit ns, 48-bit seconds */ +#define TOD_WRITE 0x0000 +/* Counter increments after TOD write is completed */ +#define TOD_WRITE_COUNTER 0x000c +/* TOD write trigger configuration */ +#define TOD_WRITE_SELECT_CFG_0 0x000d +/* TOD write trigger selection */ +#define TOD_WRITE_CMD 0x000f +#define TOD_WRITE_1 0xcc10 +#define TOD_WRITE_1_V520 0xcc20 +#define TOD_WRITE_2 0xcc20 +#define TOD_WRITE_2_V520 0xcc30 +#define TOD_WRITE_3 0xcc30 +#define TOD_WRITE_3_V520 0xcc40 + +#define TOD_READ_PRIMARY_0 0xcc40 +#define TOD_READ_PRIMARY_0_V520 0xcc50 +/* 8-bit subns, 32-bit ns, 48-bit seconds */ +#define TOD_READ_PRIMARY 0x0000 +/* Counter increments after TOD write is completed */ +#define TOD_READ_PRIMARY_COUNTER 0x000b +/* Read trigger configuration */ +#define TOD_READ_PRIMARY_SEL_CFG_0 0x000c +/* Read trigger selection */ +#define TOD_READ_PRIMARY_CMD 0x000e +#define TOD_READ_PRIMARY_CMD_V520 0x000f +#define TOD_READ_PRIMARY_1 0xcc50 +#define TOD_READ_PRIMARY_1_V520 0xcc60 +#define TOD_READ_PRIMARY_2 0xcc60 +#define TOD_READ_PRIMARY_2_V520 0xcc80 +#define TOD_READ_PRIMARY_3 0xcc80 +#define TOD_READ_PRIMARY_3_V520 0xcc90 + +#define TOD_READ_SECONDARY_0 0xcc90 +#define TOD_READ_SECONDARY_0_V520 0xcca0 +#define TOD_READ_SECONDARY_1 0xcca0 +#define TOD_READ_SECONDARY_1_V520 0xccb0 +#define TOD_READ_SECONDARY_2 0xccb0 +#define TOD_READ_SECONDARY_2_V520 0xccc0 +#define TOD_READ_SECONDARY_3 0xccc0 +#define TOD_READ_SECONDARY_3_V520 0xccd0 + +#define OUTPUT_TDC_CFG 0xccd0 +#define OUTPUT_TDC_CFG_V520 0xcce0 +#define OUTPUT_TDC_0 0xcd00 +#define OUTPUT_TDC_1 0xcd08 +#define OUTPUT_TDC_2 0xcd10 +#define OUTPUT_TDC_3 0xcd18 +#define INPUT_TDC 0xcd20 + +#define SCRATCH 0xcf50 +#define SCRATCH_V520 0xcf4c + +#define EEPROM 0xcf68 +#define EEPROM_V520 0xcf64 + +#define OTP 0xcf70 + +#define BYTE 0xcf80 + +/* Bit definitions for the MAJ_REL register */ +#define MAJOR_SHIFT (1) +#define MAJOR_MASK (0x7f) +#define PR_BUILD BIT(0) + +/* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ +#define GPIO0_LEVEL BIT(0) +#define GPIO1_LEVEL BIT(1) +#define GPIO2_LEVEL BIT(2) +#define GPIO3_LEVEL BIT(3) +#define GPIO4_LEVEL BIT(4) +#define GPIO5_LEVEL BIT(5) +#define GPIO6_LEVEL BIT(6) +#define GPIO7_LEVEL BIT(7) + +/* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ +#define GPIO8_LEVEL BIT(0) +#define GPIO9_LEVEL BIT(1) +#define GPIO10_LEVEL BIT(2) +#define GPIO11_LEVEL BIT(3) +#define GPIO12_LEVEL BIT(4) +#define GPIO13_LEVEL BIT(5) +#define GPIO14_LEVEL BIT(6) +#define GPIO15_LEVEL BIT(7) + +/* Bit definitions for the GPIO0_TO_7_OUT register */ +#define GPIO0_DRIVE_LEVEL BIT(0) +#define GPIO1_DRIVE_LEVEL BIT(1) +#define GPIO2_DRIVE_LEVEL BIT(2) +#define GPIO3_DRIVE_LEVEL BIT(3) +#define GPIO4_DRIVE_LEVEL BIT(4) +#define GPIO5_DRIVE_LEVEL BIT(5) +#define GPIO6_DRIVE_LEVEL BIT(6) +#define GPIO7_DRIVE_LEVEL BIT(7) + +/* Bit definitions for the GPIO8_TO_15_OUT register */ +#define GPIO8_DRIVE_LEVEL BIT(0) +#define GPIO9_DRIVE_LEVEL BIT(1) +#define GPIO10_DRIVE_LEVEL BIT(2) +#define GPIO11_DRIVE_LEVEL BIT(3) +#define GPIO12_DRIVE_LEVEL BIT(4) +#define GPIO13_DRIVE_LEVEL BIT(5) +#define GPIO14_DRIVE_LEVEL BIT(6) +#define GPIO15_DRIVE_LEVEL BIT(7) + +/* Bit definitions for the DPLL_TOD_SYNC_CFG register */ +#define TOD_SYNC_SOURCE_SHIFT (1) +#define TOD_SYNC_SOURCE_MASK (0x3) +#define TOD_SYNC_EN BIT(0) + +/* Bit definitions for the DPLL_MODE register */ +#define WRITE_TIMER_MODE BIT(6) +#define PLL_MODE_SHIFT (3) +#define PLL_MODE_MASK (0x7) +#define STATE_MODE_SHIFT (0) +#define STATE_MODE_MASK (0x7) + +/* Bit definitions for the GPIO_CFG_GBL register */ +#define SUPPLY_MODE_SHIFT (0) +#define SUPPLY_MODE_MASK (0x3) + +/* Bit definitions for the GPIO_DCO_INC_DEC register */ +#define INCDEC_DPLL_INDEX_SHIFT (0) +#define INCDEC_DPLL_INDEX_MASK (0x7) + +/* Bit definitions for the GPIO_OUT_CTRL_0 register */ +#define CTRL_OUT_0 BIT(0) +#define CTRL_OUT_1 BIT(1) +#define CTRL_OUT_2 BIT(2) +#define CTRL_OUT_3 BIT(3) +#define CTRL_OUT_4 BIT(4) +#define CTRL_OUT_5 BIT(5) +#define CTRL_OUT_6 BIT(6) +#define CTRL_OUT_7 BIT(7) + +/* Bit definitions for the GPIO_OUT_CTRL_1 register */ +#define CTRL_OUT_8 BIT(0) +#define CTRL_OUT_9 BIT(1) +#define CTRL_OUT_10 BIT(2) +#define CTRL_OUT_11 BIT(3) +#define CTRL_OUT_12 BIT(4) +#define CTRL_OUT_13 BIT(5) +#define CTRL_OUT_14 BIT(6) +#define CTRL_OUT_15 BIT(7) + +/* Bit definitions for the GPIO_TOD_TRIG register */ +#define TOD_TRIG_0 BIT(0) +#define TOD_TRIG_1 BIT(1) +#define TOD_TRIG_2 BIT(2) +#define TOD_TRIG_3 BIT(3) + +/* Bit definitions for the GPIO_DPLL_INDICATOR register */ +#define IND_DPLL_INDEX_SHIFT (0) +#define IND_DPLL_INDEX_MASK (0x7) + +/* Bit definitions for the GPIO_LOS_INDICATOR register */ +#define REFMON_INDEX_SHIFT (0) +#define REFMON_INDEX_MASK (0xf) +/* Active level of LOS indicator, 0=low 1=high */ +#define ACTIVE_LEVEL BIT(4) + +/* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ +#define DSQ_INP_0 BIT(0) +#define DSQ_INP_1 BIT(1) +#define DSQ_INP_2 BIT(2) +#define DSQ_INP_3 BIT(3) +#define DSQ_INP_4 BIT(4) +#define DSQ_INP_5 BIT(5) +#define DSQ_INP_6 BIT(6) +#define DSQ_INP_7 BIT(7) + +/* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ +#define DSQ_INP_8 BIT(0) +#define DSQ_INP_9 BIT(1) +#define DSQ_INP_10 BIT(2) +#define DSQ_INP_11 BIT(3) +#define DSQ_INP_12 BIT(4) +#define DSQ_INP_13 BIT(5) +#define DSQ_INP_14 BIT(6) +#define DSQ_INP_15 BIT(7) + +/* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ +#define DSQ_DPLL_0 BIT(0) +#define DSQ_DPLL_1 BIT(1) +#define DSQ_DPLL_2 BIT(2) +#define DSQ_DPLL_3 BIT(3) +#define DSQ_DPLL_4 BIT(4) +#define DSQ_DPLL_5 BIT(5) +#define DSQ_DPLL_6 BIT(6) +#define DSQ_DPLL_7 BIT(7) + +/* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ +#define DSQ_DPLL_SYS BIT(0) +#define GPIO_DSQ_LEVEL BIT(1) + +/* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ +#define DPLL_TOD_SHIFT (0) +#define DPLL_TOD_MASK (0x3) +#define TOD_READ_SECONDARY BIT(2) +#define GPIO_ASSERT_LEVEL BIT(3) + +/* Bit definitions for the GPIO_CTRL register */ +#define GPIO_FUNCTION_EN BIT(0) +#define GPIO_CMOS_OD_MODE BIT(1) +#define GPIO_CONTROL_DIR BIT(2) +#define GPIO_PU_PD_MODE BIT(3) +#define GPIO_FUNCTION_SHIFT (4) +#define GPIO_FUNCTION_MASK (0xf) + +/* Bit definitions for the OUT_CTRL_1 register */ +#define OUT_SYNC_DISABLE BIT(7) +#define SQUELCH_VALUE BIT(6) +#define SQUELCH_DISABLE BIT(5) +#define PAD_VDDO_SHIFT (2) +#define PAD_VDDO_MASK (0x7) +#define PAD_CMOSDRV_SHIFT (0) +#define PAD_CMOSDRV_MASK (0x3) + +/* Bit definitions for the TOD_CFG register */ +#define TOD_EVEN_PPS_MODE BIT(2) +#define TOD_OUT_SYNC_ENABLE BIT(1) +#define TOD_ENABLE BIT(0) + +/* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ +#define WR_PWM_DECODER_INDEX_SHIFT (4) +#define WR_PWM_DECODER_INDEX_MASK (0xf) +#define WR_REF_INDEX_SHIFT (0) +#define WR_REF_INDEX_MASK (0xf) + +/* Bit definitions for the TOD_WRITE_CMD register */ +#define TOD_WRITE_SELECTION_SHIFT (0) +#define TOD_WRITE_SELECTION_MASK (0xf) +/* 4.8.7 */ +#define TOD_WRITE_TYPE_SHIFT (4) +#define TOD_WRITE_TYPE_MASK (0x3) + +/* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ +#define RD_PWM_DECODER_INDEX_SHIFT (4) +#define RD_PWM_DECODER_INDEX_MASK (0xf) +#define RD_REF_INDEX_SHIFT (0) +#define RD_REF_INDEX_MASK (0xf) + +/* Bit definitions for the TOD_READ_PRIMARY_CMD register */ +#define TOD_READ_TRIGGER_MODE BIT(4) +#define TOD_READ_TRIGGER_SHIFT (0) +#define TOD_READ_TRIGGER_MASK (0xf) + +/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ +#define COMBO_MASTER_HOLD BIT(0) + +/* Bit definitions for DPLL_SYS_STATUS register */ +#define DPLL_SYS_STATE_MASK (0xf) + +/* Bit definitions for SYS_APLL_STATUS register */ +#define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0) +#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0 +#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1 + +/* Bit definitions for the DPLL0_STATUS register */ +#define DPLL_STATE_MASK (0xf) +#define DPLL_STATE_SHIFT (0x0) + +/* Values of DPLL_N.DPLL_MODE.PLL_MODE */ +enum pll_mode { + PLL_MODE_MIN = 0, + PLL_MODE_NORMAL = PLL_MODE_MIN, + PLL_MODE_WRITE_PHASE = 1, + PLL_MODE_WRITE_FREQUENCY = 2, + PLL_MODE_GPIO_INC_DEC = 3, + PLL_MODE_SYNTHESIS = 4, + PLL_MODE_PHASE_MEASUREMENT = 5, + PLL_MODE_DISABLED = 6, + PLL_MODE_MAX = PLL_MODE_DISABLED, +}; + +enum hw_tod_write_trig_sel { + HW_TOD_WR_TRIG_SEL_MIN = 0, + HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, + HW_TOD_WR_TRIG_SEL_RESERVED = 1, + HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, + HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, + HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, + HW_TOD_WR_TRIG_SEL_GPIO = 5, + HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, + WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, +}; + +enum scsr_read_trig_sel { + /* CANCEL CURRENT TOD READ; MODULE BECOMES IDLE - NO TRIGGER OCCURS */ + SCSR_TOD_READ_TRIG_SEL_DISABLE = 0, + /* TRIGGER IMMEDIATELY */ + SCSR_TOD_READ_TRIG_SEL_IMMEDIATE = 1, + /* TRIGGER ON RISING EDGE OF INTERNAL TOD PPS SIGNAL */ + SCSR_TOD_READ_TRIG_SEL_TODPPS = 2, + /* TRGGER ON RISING EDGE OF SELECTED REFERENCE INPUT */ + SCSR_TOD_READ_TRIG_SEL_REFCLK = 3, + /* TRIGGER ON RISING EDGE OF SELECTED PWM DECODER 1PPS OUTPUT */ + SCSR_TOD_READ_TRIG_SEL_PWMPPS = 4, + SCSR_TOD_READ_TRIG_SEL_RESERVED = 5, + /* TRIGGER WHEN WRITE FREQUENCY EVENT OCCURS */ + SCSR_TOD_READ_TRIG_SEL_WRITEFREQUENCYEVENT = 6, + /* TRIGGER ON SELECTED GPIO */ + SCSR_TOD_READ_TRIG_SEL_GPIO = 7, + SCSR_TOD_READ_TRIG_SEL_MAX = SCSR_TOD_READ_TRIG_SEL_GPIO, +}; + +/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ +enum dpll_state { + DPLL_STATE_MIN = 0, + DPLL_STATE_FREERUN = DPLL_STATE_MIN, + DPLL_STATE_LOCKACQ = 1, + DPLL_STATE_LOCKREC = 2, + DPLL_STATE_LOCKED = 3, + DPLL_STATE_HOLDOVER = 4, + DPLL_STATE_OPEN_LOOP = 5, + DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, +}; + +/* 4.8.7 only */ +enum scsr_tod_write_trig_sel { + SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, + SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, + SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, + SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, + SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, + SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, + SCSR_TOD_WR_TRIG_SEL_GPIO = 6, + SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, +}; + +/* 4.8.7 only */ +enum scsr_tod_write_type_sel { + SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, + SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, + SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, + SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, +}; +#endif diff --git a/include/linux/mfd/lp87565.h b/include/linux/mfd/lp87565.h index 5640e6088fe6..4c895072d91b 100644 --- a/include/linux/mfd/lp87565.h +++ b/include/linux/mfd/lp87565.h @@ -222,31 +222,20 @@ enum lp87565_device_type { #define LP87565_GPIO2_SEL BIT(1) #define LP87565_GPIO1_SEL BIT(0) -#define LP87565_GOIO3_OD BIT(6) -#define LP87565_GOIO2_OD BIT(5) -#define LP87565_GOIO1_OD BIT(4) -#define LP87565_GOIO3_DIR BIT(2) -#define LP87565_GOIO2_DIR BIT(1) -#define LP87565_GOIO1_DIR BIT(0) - -#define LP87565_GOIO3_IN BIT(2) -#define LP87565_GOIO2_IN BIT(1) -#define LP87565_GOIO1_IN BIT(0) - -#define LP87565_GOIO3_OUT BIT(2) -#define LP87565_GOIO2_OUT BIT(1) -#define LP87565_GOIO1_OUT BIT(0) - -enum LP87565_regulator_id { - /* BUCK's */ - LP87565_BUCK_0, - LP87565_BUCK_1, - LP87565_BUCK_2, - LP87565_BUCK_3, - LP87565_BUCK_10, - LP87565_BUCK_23, - LP87565_BUCK_3210, -}; +#define LP87565_GPIO3_OD BIT(6) +#define LP87565_GPIO2_OD BIT(5) +#define LP87565_GPIO1_OD BIT(4) +#define LP87565_GPIO3_DIR BIT(2) +#define LP87565_GPIO2_DIR BIT(1) +#define LP87565_GPIO1_DIR BIT(0) + +#define LP87565_GPIO3_IN BIT(2) +#define LP87565_GPIO2_IN BIT(1) +#define LP87565_GPIO1_IN BIT(0) + +#define LP87565_GPIO3_OUT BIT(2) +#define LP87565_GPIO2_OUT BIT(1) +#define LP87565_GPIO1_OUT BIT(0) /** * struct LP87565 - state holder for the LP87565 driver @@ -263,5 +252,6 @@ struct lp87565 { u8 rev; u8 dev_type; struct regmap *regmap; + struct gpio_desc *reset_gpio; }; #endif /* __LINUX_MFD_LP87565_H */ diff --git a/include/linux/mfd/madera/pdata.h b/include/linux/mfd/madera/pdata.h index 601cbbc10370..32e3470708ed 100644 --- a/include/linux/mfd/madera/pdata.h +++ b/include/linux/mfd/madera/pdata.h @@ -31,7 +31,7 @@ struct pinctrl_map; * @irq_flags: Mode for primary IRQ (defaults to active low) * @gpio_base: Base GPIO number * @gpio_configs: Array of GPIO configurations (See - * Documentation/driver-api/pinctl.rst) + * Documentation/driver-api/pin-control.rst) * @n_gpio_configs: Number of entries in gpio_configs * @gpsw: General purpose switch mode setting. Depends on the external * hardware connected to the switch. (See the SW1_MODE field diff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h index c5a11b7458d4..68578e2019b0 100644 --- a/include/linux/mfd/mt6358/core.h +++ b/include/linux/mfd/mt6358/core.h @@ -6,12 +6,9 @@ #ifndef __MFD_MT6358_CORE_H__ #define __MFD_MT6358_CORE_H__ -#define MT6358_REG_WIDTH 16 - struct irq_top_t { int hwirq_base; unsigned int num_int_regs; - unsigned int num_int_bits; unsigned int en_reg; unsigned int en_reg_shift; unsigned int sta_reg; @@ -25,6 +22,7 @@ struct pmic_irq_data { unsigned short top_int_status_reg; bool *enable_hwirq; bool *cache_hwirq; + const struct irq_top_t *pmic_ints; }; enum mt6358_irq_top_status_shift { @@ -146,8 +144,8 @@ enum mt6358_irq_numbers { { \ .hwirq_base = MT6358_IRQ_##sp##_BASE, \ .num_int_regs = \ - ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \ - .num_int_bits = MT6358_IRQ_##sp##_BITS, \ + ((MT6358_IRQ_##sp##_BITS - 1) / \ + MTK_PMIC_REG_WIDTH) + 1, \ .en_reg = MT6358_##sp##_TOP_INT_CON0, \ .en_reg_shift = 0x6, \ .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \ diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h index 2ad0b312aa28..201139b12140 100644 --- a/include/linux/mfd/mt6358/registers.h +++ b/include/linux/mfd/mt6358/registers.h @@ -8,6 +8,8 @@ /* PMIC Registers */ #define MT6358_SWCID 0xa +#define MT6358_TOPSTATUS 0x28 +#define MT6358_TOP_RST_MISC 0x14c #define MT6358_MISC_TOP_INT_CON0 0x188 #define MT6358_MISC_TOP_INT_STATUS0 0x194 #define MT6358_TOP_INT_STATUS0 0x19e diff --git a/include/linux/mfd/mt6359/core.h b/include/linux/mfd/mt6359/core.h new file mode 100644 index 000000000000..8d298868126d --- /dev/null +++ b/include/linux/mfd/mt6359/core.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __MFD_MT6359_CORE_H__ +#define __MFD_MT6359_CORE_H__ + +enum mt6359_irq_top_status_shift { + MT6359_BUCK_TOP = 0, + MT6359_LDO_TOP, + MT6359_PSC_TOP, + MT6359_SCK_TOP, + MT6359_BM_TOP, + MT6359_HK_TOP, + MT6359_AUD_TOP = 7, + MT6359_MISC_TOP, +}; + +enum mt6359_irq_numbers { + MT6359_IRQ_VCORE_OC = 1, + MT6359_IRQ_VGPU11_OC, + MT6359_IRQ_VGPU12_OC, + MT6359_IRQ_VMODEM_OC, + MT6359_IRQ_VPROC1_OC, + MT6359_IRQ_VPROC2_OC, + MT6359_IRQ_VS1_OC, + MT6359_IRQ_VS2_OC, + MT6359_IRQ_VPA_OC = 9, + MT6359_IRQ_VFE28_OC = 16, + MT6359_IRQ_VXO22_OC, + MT6359_IRQ_VRF18_OC, + MT6359_IRQ_VRF12_OC, + MT6359_IRQ_VEFUSE_OC, + MT6359_IRQ_VCN33_1_OC, + MT6359_IRQ_VCN33_2_OC, + MT6359_IRQ_VCN13_OC, + MT6359_IRQ_VCN18_OC, + MT6359_IRQ_VA09_OC, + MT6359_IRQ_VCAMIO_OC, + MT6359_IRQ_VA12_OC, + MT6359_IRQ_VAUX18_OC, + MT6359_IRQ_VAUD18_OC, + MT6359_IRQ_VIO18_OC, + MT6359_IRQ_VSRAM_PROC1_OC, + MT6359_IRQ_VSRAM_PROC2_OC, + MT6359_IRQ_VSRAM_OTHERS_OC, + MT6359_IRQ_VSRAM_MD_OC, + MT6359_IRQ_VEMC_OC, + MT6359_IRQ_VSIM1_OC, + MT6359_IRQ_VSIM2_OC, + MT6359_IRQ_VUSB_OC, + MT6359_IRQ_VRFCK_OC, + MT6359_IRQ_VBBCK_OC, + MT6359_IRQ_VBIF28_OC, + MT6359_IRQ_VIBR_OC, + MT6359_IRQ_VIO28_OC, + MT6359_IRQ_VM18_OC, + MT6359_IRQ_VUFS_OC = 45, + MT6359_IRQ_PWRKEY = 48, + MT6359_IRQ_HOMEKEY, + MT6359_IRQ_PWRKEY_R, + MT6359_IRQ_HOMEKEY_R, + MT6359_IRQ_NI_LBAT_INT, + MT6359_IRQ_CHRDET_EDGE = 53, + MT6359_IRQ_RTC = 64, + MT6359_IRQ_FG_BAT_H = 80, + MT6359_IRQ_FG_BAT_L, + MT6359_IRQ_FG_CUR_H, + MT6359_IRQ_FG_CUR_L, + MT6359_IRQ_FG_ZCV = 84, + MT6359_IRQ_FG_N_CHARGE_L = 87, + MT6359_IRQ_FG_IAVG_H, + MT6359_IRQ_FG_IAVG_L = 89, + MT6359_IRQ_FG_DISCHARGE = 91, + MT6359_IRQ_FG_CHARGE, + MT6359_IRQ_BATON_LV = 96, + MT6359_IRQ_BATON_BAT_IN = 98, + MT6359_IRQ_BATON_BAT_OU, + MT6359_IRQ_BIF = 100, + MT6359_IRQ_BAT_H = 112, + MT6359_IRQ_BAT_L, + MT6359_IRQ_BAT2_H, + MT6359_IRQ_BAT2_L, + MT6359_IRQ_BAT_TEMP_H, + MT6359_IRQ_BAT_TEMP_L, + MT6359_IRQ_THR_H, + MT6359_IRQ_THR_L, + MT6359_IRQ_AUXADC_IMP, + MT6359_IRQ_NAG_C_DLTV = 121, + MT6359_IRQ_AUDIO = 128, + MT6359_IRQ_ACCDET = 133, + MT6359_IRQ_ACCDET_EINT0, + MT6359_IRQ_ACCDET_EINT1, + MT6359_IRQ_SPI_CMD_ALERT = 144, + MT6359_IRQ_NR, +}; + +#define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC +#define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC +#define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY +#define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC +#define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H +#define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H +#define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO +#define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT + +#define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1) +#define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1) +#define MT6359_IRQ_PSC_BITS \ + (MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1) +#define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1) +#define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1) +#define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1) +#define MT6359_IRQ_AUD_BITS \ + (MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1) +#define MT6359_IRQ_MISC_BITS \ + (MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1) + +#define MT6359_TOP_GEN(sp) \ +{ \ + .hwirq_base = MT6359_IRQ_##sp##_BASE, \ + .num_int_regs = \ + ((MT6359_IRQ_##sp##_BITS - 1) / \ + MTK_PMIC_REG_WIDTH) + 1, \ + .en_reg = MT6359_##sp##_TOP_INT_CON0, \ + .en_reg_shift = 0x6, \ + .sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \ + .sta_reg_shift = 0x2, \ + .top_offset = MT6359_##sp##_TOP, \ +} + +#endif /* __MFD_MT6359_CORE_H__ */ diff --git a/include/linux/mfd/mt6359/registers.h b/include/linux/mfd/mt6359/registers.h new file mode 100644 index 000000000000..2135c9695918 --- /dev/null +++ b/include/linux/mfd/mt6359/registers.h @@ -0,0 +1,529 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __MFD_MT6359_REGISTERS_H__ +#define __MFD_MT6359_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6359_SWCID 0xa +#define MT6359_MISC_TOP_INT_CON0 0x188 +#define MT6359_MISC_TOP_INT_STATUS0 0x194 +#define MT6359_TOP_INT_STATUS0 0x19e +#define MT6359_SCK_TOP_INT_CON0 0x528 +#define MT6359_SCK_TOP_INT_STATUS0 0x534 +#define MT6359_EOSC_CALI_CON0 0x53a +#define MT6359_EOSC_CALI_CON1 0x53c +#define MT6359_RTC_MIX_CON0 0x53e +#define MT6359_RTC_MIX_CON1 0x540 +#define MT6359_RTC_MIX_CON2 0x542 +#define MT6359_RTC_DSN_ID 0x580 +#define MT6359_RTC_DSN_REV0 0x582 +#define MT6359_RTC_DBI 0x584 +#define MT6359_RTC_DXI 0x586 +#define MT6359_RTC_BBPU 0x588 +#define MT6359_RTC_IRQ_STA 0x58a +#define MT6359_RTC_IRQ_EN 0x58c +#define MT6359_RTC_CII_EN 0x58e +#define MT6359_RTC_AL_MASK 0x590 +#define MT6359_RTC_TC_SEC 0x592 +#define MT6359_RTC_TC_MIN 0x594 +#define MT6359_RTC_TC_HOU 0x596 +#define MT6359_RTC_TC_DOM 0x598 +#define MT6359_RTC_TC_DOW 0x59a +#define MT6359_RTC_TC_MTH 0x59c +#define MT6359_RTC_TC_YEA 0x59e +#define MT6359_RTC_AL_SEC 0x5a0 +#define MT6359_RTC_AL_MIN 0x5a2 +#define MT6359_RTC_AL_HOU 0x5a4 +#define MT6359_RTC_AL_DOM 0x5a6 +#define MT6359_RTC_AL_DOW 0x5a8 +#define MT6359_RTC_AL_MTH 0x5aa +#define MT6359_RTC_AL_YEA 0x5ac +#define MT6359_RTC_OSC32CON 0x5ae +#define MT6359_RTC_POWERKEY1 0x5b0 +#define MT6359_RTC_POWERKEY2 0x5b2 +#define MT6359_RTC_PDN1 0x5b4 +#define MT6359_RTC_PDN2 0x5b6 +#define MT6359_RTC_SPAR0 0x5b8 +#define MT6359_RTC_SPAR1 0x5ba +#define MT6359_RTC_PROT 0x5bc +#define MT6359_RTC_DIFF 0x5be +#define MT6359_RTC_CALI 0x5c0 +#define MT6359_RTC_WRTGR 0x5c2 +#define MT6359_RTC_CON 0x5c4 +#define MT6359_RTC_SEC_CTRL 0x5c6 +#define MT6359_RTC_INT_CNT 0x5c8 +#define MT6359_RTC_SEC_DAT0 0x5ca +#define MT6359_RTC_SEC_DAT1 0x5cc +#define MT6359_RTC_SEC_DAT2 0x5ce +#define MT6359_RTC_SEC_DSN_ID 0x600 +#define MT6359_RTC_SEC_DSN_REV0 0x602 +#define MT6359_RTC_SEC_DBI 0x604 +#define MT6359_RTC_SEC_DXI 0x606 +#define MT6359_RTC_TC_SEC_SEC 0x608 +#define MT6359_RTC_TC_MIN_SEC 0x60a +#define MT6359_RTC_TC_HOU_SEC 0x60c +#define MT6359_RTC_TC_DOM_SEC 0x60e +#define MT6359_RTC_TC_DOW_SEC 0x610 +#define MT6359_RTC_TC_MTH_SEC 0x612 +#define MT6359_RTC_TC_YEA_SEC 0x614 +#define MT6359_RTC_SEC_CK_PDN 0x616 +#define MT6359_RTC_SEC_WRTGR 0x618 +#define MT6359_PSC_TOP_INT_CON0 0x910 +#define MT6359_PSC_TOP_INT_STATUS0 0x91c +#define MT6359_BM_TOP_INT_CON0 0xc32 +#define MT6359_BM_TOP_INT_CON1 0xc38 +#define MT6359_BM_TOP_INT_STATUS0 0xc4a +#define MT6359_BM_TOP_INT_STATUS1 0xc4c +#define MT6359_HK_TOP_INT_CON0 0xf92 +#define MT6359_HK_TOP_INT_STATUS0 0xf9e +#define MT6359_BUCK_TOP_INT_CON0 0x1418 +#define MT6359_BUCK_TOP_INT_STATUS0 0x1424 +#define MT6359_BUCK_VPU_CON0 0x1488 +#define MT6359_BUCK_VPU_DBG0 0x14a6 +#define MT6359_BUCK_VPU_DBG1 0x14a8 +#define MT6359_BUCK_VPU_ELR0 0x14ac +#define MT6359_BUCK_VCORE_CON0 0x1508 +#define MT6359_BUCK_VCORE_DBG0 0x1526 +#define MT6359_BUCK_VCORE_DBG1 0x1528 +#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a +#define MT6359_BUCK_VCORE_ELR0 0x1534 +#define MT6359_BUCK_VGPU11_CON0 0x1588 +#define MT6359_BUCK_VGPU11_DBG0 0x15a6 +#define MT6359_BUCK_VGPU11_DBG1 0x15a8 +#define MT6359_BUCK_VGPU11_ELR0 0x15ac +#define MT6359_BUCK_VMODEM_CON0 0x1688 +#define MT6359_BUCK_VMODEM_DBG0 0x16a6 +#define MT6359_BUCK_VMODEM_DBG1 0x16a8 +#define MT6359_BUCK_VMODEM_ELR0 0x16ae +#define MT6359_BUCK_VPROC1_CON0 0x1708 +#define MT6359_BUCK_VPROC1_DBG0 0x1726 +#define MT6359_BUCK_VPROC1_DBG1 0x1728 +#define MT6359_BUCK_VPROC1_ELR0 0x172e +#define MT6359_BUCK_VPROC2_CON0 0x1788 +#define MT6359_BUCK_VPROC2_DBG0 0x17a6 +#define MT6359_BUCK_VPROC2_DBG1 0x17a8 +#define MT6359_BUCK_VPROC2_ELR0 0x17b2 +#define MT6359_BUCK_VS1_CON0 0x1808 +#define MT6359_BUCK_VS1_DBG0 0x1826 +#define MT6359_BUCK_VS1_DBG1 0x1828 +#define MT6359_BUCK_VS1_ELR0 0x1834 +#define MT6359_BUCK_VS2_CON0 0x1888 +#define MT6359_BUCK_VS2_DBG0 0x18a6 +#define MT6359_BUCK_VS2_DBG1 0x18a8 +#define MT6359_BUCK_VS2_ELR0 0x18b4 +#define MT6359_BUCK_VPA_CON0 0x1908 +#define MT6359_BUCK_VPA_CON1 0x190e +#define MT6359_BUCK_VPA_CFG0 0x1910 +#define MT6359_BUCK_VPA_CFG1 0x1912 +#define MT6359_BUCK_VPA_DBG0 0x1914 +#define MT6359_BUCK_VPA_DBG1 0x1916 +#define MT6359_VGPUVCORE_ANA_CON2 0x198e +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4 +#define MT6359_VPROC1_ANA_CON3 0x19b2 +#define MT6359_VPROC2_ANA_CON3 0x1a0e +#define MT6359_VMODEM_ANA_CON3 0x1a1a +#define MT6359_VPU_ANA_CON3 0x1a26 +#define MT6359_VS1_ANA_CON0 0x1a2c +#define MT6359_VS2_ANA_CON0 0x1a34 +#define MT6359_VPA_ANA_CON0 0x1a3c +#define MT6359_LDO_TOP_INT_CON0 0x1b14 +#define MT6359_LDO_TOP_INT_CON1 0x1b1a +#define MT6359_LDO_TOP_INT_STATUS0 0x1b28 +#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a +#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40 +#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42 +#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44 +#define MT6359_LDO_VSRAM_MD_ELR 0x1b46 +#define MT6359_LDO_VFE28_CON0 0x1b88 +#define MT6359_LDO_VFE28_MON 0x1b8a +#define MT6359_LDO_VXO22_CON0 0x1b98 +#define MT6359_LDO_VXO22_MON 0x1b9a +#define MT6359_LDO_VRF18_CON0 0x1ba8 +#define MT6359_LDO_VRF18_MON 0x1baa +#define MT6359_LDO_VRF12_CON0 0x1bb8 +#define MT6359_LDO_VRF12_MON 0x1bba +#define MT6359_LDO_VEFUSE_CON0 0x1bc8 +#define MT6359_LDO_VEFUSE_MON 0x1bca +#define MT6359_LDO_VCN33_1_CON0 0x1bd8 +#define MT6359_LDO_VCN33_1_MON 0x1bda +#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8 +#define MT6359_LDO_VCN33_2_CON0 0x1c08 +#define MT6359_LDO_VCN33_2_MON 0x1c0a +#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18 +#define MT6359_LDO_VCN13_CON0 0x1c1a +#define MT6359_LDO_VCN13_MON 0x1c1c +#define MT6359_LDO_VCN18_CON0 0x1c2a +#define MT6359_LDO_VCN18_MON 0x1c2c +#define MT6359_LDO_VA09_CON0 0x1c3a +#define MT6359_LDO_VA09_MON 0x1c3c +#define MT6359_LDO_VCAMIO_CON0 0x1c4a +#define MT6359_LDO_VCAMIO_MON 0x1c4c +#define MT6359_LDO_VA12_CON0 0x1c5a +#define MT6359_LDO_VA12_MON 0x1c5c +#define MT6359_LDO_VAUX18_CON0 0x1c88 +#define MT6359_LDO_VAUX18_MON 0x1c8a +#define MT6359_LDO_VAUD18_CON0 0x1c98 +#define MT6359_LDO_VAUD18_MON 0x1c9a +#define MT6359_LDO_VIO18_CON0 0x1ca8 +#define MT6359_LDO_VIO18_MON 0x1caa +#define MT6359_LDO_VEMC_CON0 0x1cb8 +#define MT6359_LDO_VEMC_MON 0x1cba +#define MT6359_LDO_VSIM1_CON0 0x1cc8 +#define MT6359_LDO_VSIM1_MON 0x1cca +#define MT6359_LDO_VSIM2_CON0 0x1cd8 +#define MT6359_LDO_VSIM2_MON 0x1cda +#define MT6359_LDO_VUSB_CON0 0x1d08 +#define MT6359_LDO_VUSB_MON 0x1d0a +#define MT6359_LDO_VUSB_MULTI_SW 0x1d18 +#define MT6359_LDO_VRFCK_CON0 0x1d1a +#define MT6359_LDO_VRFCK_MON 0x1d1c +#define MT6359_LDO_VBBCK_CON0 0x1d2a +#define MT6359_LDO_VBBCK_MON 0x1d2c +#define MT6359_LDO_VBIF28_CON0 0x1d3a +#define MT6359_LDO_VBIF28_MON 0x1d3c +#define MT6359_LDO_VIBR_CON0 0x1d4a +#define MT6359_LDO_VIBR_MON 0x1d4c +#define MT6359_LDO_VIO28_CON0 0x1d5a +#define MT6359_LDO_VIO28_MON 0x1d5c +#define MT6359_LDO_VM18_CON0 0x1d88 +#define MT6359_LDO_VM18_MON 0x1d8a +#define MT6359_LDO_VUFS_CON0 0x1d98 +#define MT6359_LDO_VUFS_MON 0x1d9a +#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88 +#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a +#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e +#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6 +#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8 +#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac +#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08 +#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a +#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e +#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26 +#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c +#define MT6359_LDO_VSRAM_MD_MON 0x1f2e +#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32 +#define MT6359_VFE28_ANA_CON0 0x1f88 +#define MT6359_VAUX18_ANA_CON0 0x1f8c +#define MT6359_VUSB_ANA_CON0 0x1f90 +#define MT6359_VBIF28_ANA_CON0 0x1f94 +#define MT6359_VCN33_1_ANA_CON0 0x1f98 +#define MT6359_VCN33_2_ANA_CON0 0x1f9c +#define MT6359_VEMC_ANA_CON0 0x1fa0 +#define MT6359_VSIM1_ANA_CON0 0x1fa4 +#define MT6359_VSIM2_ANA_CON0 0x1fa8 +#define MT6359_VIO28_ANA_CON0 0x1fac +#define MT6359_VIBR_ANA_CON0 0x1fb0 +#define MT6359_VRF18_ANA_CON0 0x2008 +#define MT6359_VEFUSE_ANA_CON0 0x200c +#define MT6359_VCN18_ANA_CON0 0x2010 +#define MT6359_VCAMIO_ANA_CON0 0x2014 +#define MT6359_VAUD18_ANA_CON0 0x2018 +#define MT6359_VIO18_ANA_CON0 0x201c +#define MT6359_VM18_ANA_CON0 0x2020 +#define MT6359_VUFS_ANA_CON0 0x2024 +#define MT6359_VRF12_ANA_CON0 0x202a +#define MT6359_VCN13_ANA_CON0 0x202e +#define MT6359_VA09_ANA_CON0 0x2032 +#define MT6359_VA12_ANA_CON0 0x2036 +#define MT6359_VXO22_ANA_CON0 0x2088 +#define MT6359_VRFCK_ANA_CON0 0x208c +#define MT6359_VBBCK_ANA_CON0 0x2094 +#define MT6359_AUD_TOP_INT_CON0 0x2328 +#define MT6359_AUD_TOP_INT_STATUS0 0x2334 + +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1 +#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0 +#define MT6359_DA_VPU_VOSEL_MASK 0x7F +#define MT6359_DA_VPU_VOSEL_SHIFT 0 +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 +#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0 +#define MT6359_DA_VCORE_VOSEL_MASK 0x7F +#define MT6359_DA_VCORE_VOSEL_SHIFT 0 +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 +#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4 +#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0 +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 +#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0 +#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F +#define MT6359_DA_VGPU11_VOSEL_SHIFT 0 +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 +#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0 +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 +#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0 +#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F +#define MT6359_DA_VMODEM_VOSEL_SHIFT 0 +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 +#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0 +#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F +#define MT6359_DA_VPROC1_VOSEL_SHIFT 0 +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 +#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0 +#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F +#define MT6359_DA_VPROC2_VOSEL_SHIFT 0 +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1 +#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0 +#define MT6359_DA_VS1_VOSEL_MASK 0x7F +#define MT6359_DA_VS1_VOSEL_SHIFT 0 +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1 +#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0 +#define MT6359_DA_VS2_VOSEL_MASK 0x7F +#define MT6359_DA_VS2_VOSEL_SHIFT 0 +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1 +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 +#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0 +#define MT6359_DA_VPA_VOSEL_MASK 0x3F +#define MT6359_DA_VPA_VOSEL_SHIFT 0 +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 +#define MT6359_RG_VGPU11_FCCM_SHIFT 9 +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 +#define MT6359_RG_VCORE_FCCM_SHIFT 5 +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 +#define MT6359_RG_VPROC1_FCCM_SHIFT 1 +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 +#define MT6359_RG_VPROC2_FCCM_SHIFT 1 +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 +#define MT6359_RG_VMODEM_FCCM_SHIFT 1 +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 +#define MT6359_RG_VPU_FCCM_SHIFT 1 +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 +#define MT6359_RG_VS1_FPWM_SHIFT 3 +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 +#define MT6359_RG_VS2_FPWM_SHIFT 3 +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 +#define MT6359_RG_VPA_MODESET_SHIFT 1 +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0 +#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON +#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0 +#define MT6359_RG_LDO_VXO22_EN_SHIFT 0 +#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON +#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0 +#define MT6359_RG_LDO_VRF18_EN_SHIFT 0 +#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON +#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0 +#define MT6359_RG_LDO_VRF12_EN_SHIFT 0 +#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON +#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0 +#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0 +#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON +#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0 +#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1 +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 +#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON +#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW +#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0 +#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0 +#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON +#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW +#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1 +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0 +#define MT6359_RG_LDO_VCN13_EN_SHIFT 0 +#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON +#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0 +#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON +#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0 +#define MT6359_RG_LDO_VA09_EN_SHIFT 0 +#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON +#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0 +#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0 +#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON +#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0 +#define MT6359_RG_LDO_VA12_EN_SHIFT 0 +#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON +#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0 +#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON +#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0 +#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON +#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0 +#define MT6359_RG_LDO_VIO18_EN_SHIFT 0 +#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON +#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0 +#define MT6359_RG_LDO_VEMC_EN_SHIFT 0 +#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON +#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0 +#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0 +#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON +#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0 +#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0 +#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON +#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0 +#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1 +#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0 +#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON +#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW +#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1 +#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0 +#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0 +#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON +#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0 +#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0 +#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON +#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0 +#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON +#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0 +#define MT6359_RG_LDO_VIBR_EN_SHIFT 0 +#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON +#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0 +#define MT6359_RG_LDO_VIO28_EN_SHIFT 0 +#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON +#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0 +#define MT6359_RG_LDO_VM18_EN_SHIFT 0 +#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON +#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0 +#define MT6359_RG_LDO_VUFS_EN_SHIFT 0 +#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON +#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0 +#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON +#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1 +#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F +#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8 +#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0 +#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON +#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1 +#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F +#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8 +#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0 +#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON +#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1 +#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F +#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8 +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 +#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0 +#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON +#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1 +#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F +#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8 +#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0 +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 +#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0 +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 +#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0 +#define MT6359_RG_VEMC_VOSEL_MASK 0xF +#define MT6359_RG_VEMC_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0 +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0 +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8 +#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0 +#define MT6359_RG_VIO28_VOSEL_MASK 0xF +#define MT6359_RG_VIO28_VOSEL_SHIFT 8 +#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0 +#define MT6359_RG_VIBR_VOSEL_MASK 0xF +#define MT6359_RG_VIBR_VOSEL_SHIFT 8 +#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0 +#define MT6359_RG_VRF18_VOSEL_MASK 0xF +#define MT6359_RG_VRF18_VOSEL_SHIFT 8 +#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0 +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 +#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0 +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 +#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0 +#define MT6359_RG_VIO18_VOSEL_MASK 0xF +#define MT6359_RG_VIO18_VOSEL_SHIFT 8 +#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0 +#define MT6359_RG_VM18_VOSEL_MASK 0xF +#define MT6359_RG_VM18_VOSEL_SHIFT 8 +#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0 +#define MT6359_RG_VUFS_VOSEL_MASK 0xF +#define MT6359_RG_VUFS_VOSEL_SHIFT 8 +#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0 +#define MT6359_RG_VRF12_VOSEL_MASK 0xF +#define MT6359_RG_VRF12_VOSEL_SHIFT 8 +#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0 +#define MT6359_RG_VCN13_VOSEL_MASK 0xF +#define MT6359_RG_VCN13_VOSEL_SHIFT 8 +#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0 +#define MT6359_RG_VA09_VOSEL_MASK 0xF +#define MT6359_RG_VA09_VOSEL_SHIFT 8 +#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0 +#define MT6359_RG_VA12_VOSEL_MASK 0xF +#define MT6359_RG_VA12_VOSEL_SHIFT 8 +#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0 +#define MT6359_RG_VXO22_VOSEL_MASK 0xF +#define MT6359_RG_VXO22_VOSEL_SHIFT 8 +#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0 +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8 +#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0 +#define MT6359_RG_VBBCK_VOSEL_MASK 0xF +#define MT6359_RG_VBBCK_VOSEL_SHIFT 8 + +#endif /* __MFD_MT6359_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6359p/registers.h b/include/linux/mfd/mt6359p/registers.h new file mode 100644 index 000000000000..3d97c1885171 --- /dev/null +++ b/include/linux/mfd/mt6359p/registers.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __MFD_MT6359P_REGISTERS_H__ +#define __MFD_MT6359P_REGISTERS_H__ + +#define MT6359P_CHIP_VER 0x5930 + +/* PMIC Registers */ +#define MT6359P_HWCID 0x8 +#define MT6359P_TOP_TRAP 0x50 +#define MT6359P_TOP_TMA_KEY 0x3a8 +#define MT6359P_BUCK_VCORE_ELR_NUM 0x152a +#define MT6359P_BUCK_VCORE_ELR0 0x152c +#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa +#define MT6359P_BUCK_VGPU11_ELR0 0x15b4 +#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 +#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 +#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 +#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a +#define MT6359P_LDO_VEMC_ELR_0 0x1b4c +#define MT6359P_LDO_VFE28_CON0 0x1b88 +#define MT6359P_LDO_VFE28_MON 0x1b8c +#define MT6359P_LDO_VXO22_CON0 0x1b9a +#define MT6359P_LDO_VXO22_MON 0x1b9e +#define MT6359P_LDO_VRF18_CON0 0x1bac +#define MT6359P_LDO_VRF18_MON 0x1bb0 +#define MT6359P_LDO_VRF12_CON0 0x1bbe +#define MT6359P_LDO_VRF12_MON 0x1bc2 +#define MT6359P_LDO_VEFUSE_CON0 0x1bd0 +#define MT6359P_LDO_VEFUSE_MON 0x1bd4 +#define MT6359P_LDO_VCN33_1_CON0 0x1be2 +#define MT6359P_LDO_VCN33_1_MON 0x1be6 +#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 +#define MT6359P_LDO_VCN33_2_CON0 0x1c08 +#define MT6359P_LDO_VCN33_2_MON 0x1c0c +#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a +#define MT6359P_LDO_VCN13_CON0 0x1c1c +#define MT6359P_LDO_VCN13_MON 0x1c20 +#define MT6359P_LDO_VCN18_CON0 0x1c2e +#define MT6359P_LDO_VCN18_MON 0x1c32 +#define MT6359P_LDO_VA09_CON0 0x1c40 +#define MT6359P_LDO_VA09_MON 0x1c44 +#define MT6359P_LDO_VCAMIO_CON0 0x1c52 +#define MT6359P_LDO_VCAMIO_MON 0x1c56 +#define MT6359P_LDO_VA12_CON0 0x1c64 +#define MT6359P_LDO_VA12_MON 0x1c68 +#define MT6359P_LDO_VAUX18_CON0 0x1c88 +#define MT6359P_LDO_VAUX18_MON 0x1c8c +#define MT6359P_LDO_VAUD18_CON0 0x1c9a +#define MT6359P_LDO_VAUD18_MON 0x1c9e +#define MT6359P_LDO_VIO18_CON0 0x1cac +#define MT6359P_LDO_VIO18_MON 0x1cb0 +#define MT6359P_LDO_VEMC_CON0 0x1cbe +#define MT6359P_LDO_VEMC_MON 0x1cc2 +#define MT6359P_LDO_VSIM1_CON0 0x1cd0 +#define MT6359P_LDO_VSIM1_MON 0x1cd4 +#define MT6359P_LDO_VSIM2_CON0 0x1ce2 +#define MT6359P_LDO_VSIM2_MON 0x1ce6 +#define MT6359P_LDO_VUSB_CON0 0x1d08 +#define MT6359P_LDO_VUSB_MON 0x1d0c +#define MT6359P_LDO_VUSB_MULTI_SW 0x1d1a +#define MT6359P_LDO_VRFCK_CON0 0x1d1c +#define MT6359P_LDO_VRFCK_MON 0x1d20 +#define MT6359P_LDO_VBBCK_CON0 0x1d2e +#define MT6359P_LDO_VBBCK_MON 0x1d32 +#define MT6359P_LDO_VBIF28_CON0 0x1d40 +#define MT6359P_LDO_VBIF28_MON 0x1d44 +#define MT6359P_LDO_VIBR_CON0 0x1d52 +#define MT6359P_LDO_VIBR_MON 0x1d56 +#define MT6359P_LDO_VIO28_CON0 0x1d64 +#define MT6359P_LDO_VIO28_MON 0x1d68 +#define MT6359P_LDO_VM18_CON0 0x1d88 +#define MT6359P_LDO_VM18_MON 0x1d8c +#define MT6359P_LDO_VUFS_CON0 0x1d9a +#define MT6359P_LDO_VUFS_MON 0x1d9e +#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 +#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c +#define MT6359P_LDO_VSRAM_PROC1_VOSEL1 0x1e90 +#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 +#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac +#define MT6359P_LDO_VSRAM_PROC2_VOSEL1 0x1eb0 +#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 +#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c +#define MT6359P_LDO_VSRAM_OTHERS_VOSEL1 0x1f10 +#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 +#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e +#define MT6359P_LDO_VSRAM_MD_MON 0x1f32 +#define MT6359P_LDO_VSRAM_MD_VOSEL1 0x1f36 +#define MT6359P_VFE28_ANA_CON0 0x1f88 +#define MT6359P_VAUX18_ANA_CON0 0x1f8c +#define MT6359P_VUSB_ANA_CON0 0x1f90 +#define MT6359P_VBIF28_ANA_CON0 0x1f94 +#define MT6359P_VCN33_1_ANA_CON0 0x1f98 +#define MT6359P_VCN33_2_ANA_CON0 0x1f9c +#define MT6359P_VEMC_ANA_CON0 0x1fa0 +#define MT6359P_VSIM1_ANA_CON0 0x1fa2 +#define MT6359P_VSIM2_ANA_CON0 0x1fa6 +#define MT6359P_VIO28_ANA_CON0 0x1faa +#define MT6359P_VIBR_ANA_CON0 0x1fae +#define MT6359P_VFE28_ELR_4 0x1fc0 +#define MT6359P_VRF18_ANA_CON0 0x2008 +#define MT6359P_VEFUSE_ANA_CON0 0x200c +#define MT6359P_VCN18_ANA_CON0 0x2010 +#define MT6359P_VCAMIO_ANA_CON0 0x2014 +#define MT6359P_VAUD18_ANA_CON0 0x2018 +#define MT6359P_VIO18_ANA_CON0 0x201c +#define MT6359P_VM18_ANA_CON0 0x2020 +#define MT6359P_VUFS_ANA_CON0 0x2024 +#define MT6359P_VRF12_ANA_CON0 0x202a +#define MT6359P_VCN13_ANA_CON0 0x202e +#define MT6359P_VA09_ANA_CON0 0x2032 +#define MT6359P_VRF18_ELR_3 0x204e +#define MT6359P_VXO22_ANA_CON0 0x2088 +#define MT6359P_VRFCK_ANA_CON0 0x208c +#define MT6359P_VBBCK_ANA_CON0 0x2096 + +#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR +#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 +#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF +#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 +#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 +#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON +#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 +#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 +#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON +#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 +#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 +#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON +#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 +#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 +#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON +#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 +#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 +#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON +#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 +#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON +#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW +#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 +#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 +#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 +#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON +#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW +#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 +#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 +#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON +#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 +#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON +#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 +#define MT6359P_RG_LDO_VA09_EN_SHIFT 0 +#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON +#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 +#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 +#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON +#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 +#define MT6359P_RG_LDO_VA12_EN_SHIFT 0 +#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON +#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 +#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON +#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 +#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON +#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 +#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 +#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON +#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 +#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 +#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON +#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 +#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 +#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON +#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 +#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 +#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON +#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 +#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON +#define MT6359P_RG_LDO_VUSB_EN_1_ADDR MT6359P_LDO_VUSB_MULTI_SW +#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 +#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 +#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON +#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 +#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 +#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON +#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 +#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON +#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 +#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 +#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON +#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 +#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 +#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON +#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 +#define MT6359P_RG_LDO_VM18_EN_SHIFT 0 +#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON +#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 +#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 +#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON +#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 +#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON +#define MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_VOSEL1 +#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 +#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON +#define MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_VOSEL1 +#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 +#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON +#define MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_VOSEL1 +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 +#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON +#define MT6359P_DA_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_VOSEL1 +#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 +#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 +#define MT6359P_RG_VEMC_VOSEL_ADDR MT6359P_VEMC_ANA_CON0 +#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 +#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 +#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 +#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 +#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 +#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 +#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 +#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 +#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 +#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 +#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 +#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 +#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3 +#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 +#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 +#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF +#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4 +#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP +#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY + +#define TMA_KEY 0x9CA6 + +#endif /* __MFD_MT6359P_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h deleted file mode 100644 index ea1304035d4d..000000000000 --- a/include/linux/mfd/mt6360.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - */ - -#ifndef __MT6360_H__ -#define __MT6360_H__ - -#include <linux/regmap.h> - -enum { - MT6360_SLAVE_PMU = 0, - MT6360_SLAVE_PMIC, - MT6360_SLAVE_LDO, - MT6360_SLAVE_TCPC, - MT6360_SLAVE_MAX, -}; - -#define MT6360_PMU_SLAVEID (0x34) -#define MT6360_PMIC_SLAVEID (0x1A) -#define MT6360_LDO_SLAVEID (0x64) -#define MT6360_TCPC_SLAVEID (0x4E) - -struct mt6360_pmu_data { - struct i2c_client *i2c[MT6360_SLAVE_MAX]; - struct device *dev; - struct regmap *regmap; - struct regmap_irq_chip_data *irq_data; - unsigned int chip_rev; -}; - -/* PMU register defininition */ -#define MT6360_PMU_DEV_INFO (0x00) -#define MT6360_PMU_CORE_CTRL1 (0x01) -#define MT6360_PMU_RST1 (0x02) -#define MT6360_PMU_CRCEN (0x03) -#define MT6360_PMU_RST_PAS_CODE1 (0x04) -#define MT6360_PMU_RST_PAS_CODE2 (0x05) -#define MT6360_PMU_CORE_CTRL2 (0x06) -#define MT6360_PMU_TM_PAS_CODE1 (0x07) -#define MT6360_PMU_TM_PAS_CODE2 (0x08) -#define MT6360_PMU_TM_PAS_CODE3 (0x09) -#define MT6360_PMU_TM_PAS_CODE4 (0x0A) -#define MT6360_PMU_IRQ_IND (0x0B) -#define MT6360_PMU_IRQ_MASK (0x0C) -#define MT6360_PMU_IRQ_SET (0x0D) -#define MT6360_PMU_SHDN_CTRL (0x0E) -#define MT6360_PMU_TM_INF (0x0F) -#define MT6360_PMU_I2C_CTRL (0x10) -#define MT6360_PMU_CHG_CTRL1 (0x11) -#define MT6360_PMU_CHG_CTRL2 (0x12) -#define MT6360_PMU_CHG_CTRL3 (0x13) -#define MT6360_PMU_CHG_CTRL4 (0x14) -#define MT6360_PMU_CHG_CTRL5 (0x15) -#define MT6360_PMU_CHG_CTRL6 (0x16) -#define MT6360_PMU_CHG_CTRL7 (0x17) -#define MT6360_PMU_CHG_CTRL8 (0x18) -#define MT6360_PMU_CHG_CTRL9 (0x19) -#define MT6360_PMU_CHG_CTRL10 (0x1A) -#define MT6360_PMU_CHG_CTRL11 (0x1B) -#define MT6360_PMU_CHG_CTRL12 (0x1C) -#define MT6360_PMU_CHG_CTRL13 (0x1D) -#define MT6360_PMU_CHG_CTRL14 (0x1E) -#define MT6360_PMU_CHG_CTRL15 (0x1F) -#define MT6360_PMU_CHG_CTRL16 (0x20) -#define MT6360_PMU_CHG_AICC_RESULT (0x21) -#define MT6360_PMU_DEVICE_TYPE (0x22) -#define MT6360_PMU_QC_CONTROL1 (0x23) -#define MT6360_PMU_QC_CONTROL2 (0x24) -#define MT6360_PMU_QC30_CONTROL1 (0x25) -#define MT6360_PMU_QC30_CONTROL2 (0x26) -#define MT6360_PMU_USB_STATUS1 (0x27) -#define MT6360_PMU_QC_STATUS1 (0x28) -#define MT6360_PMU_QC_STATUS2 (0x29) -#define MT6360_PMU_CHG_PUMP (0x2A) -#define MT6360_PMU_CHG_CTRL17 (0x2B) -#define MT6360_PMU_CHG_CTRL18 (0x2C) -#define MT6360_PMU_CHRDET_CTRL1 (0x2D) -#define MT6360_PMU_CHRDET_CTRL2 (0x2E) -#define MT6360_PMU_DPDN_CTRL (0x2F) -#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) -#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) -#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) -#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) -#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) -#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) -#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) -#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) -#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) -#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) -#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) -#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) -#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) -#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) -#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) -#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) -#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) -#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) -#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) -#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) -#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) -#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) -#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) -#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) -#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) -#define MT6360_PMU_BC12_CTRL (0x49) -#define MT6360_PMU_CHG_STAT (0x4A) -#define MT6360_PMU_RESV1 (0x4B) -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) -#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) -#define MT6360_PMU_TYPEC_OTP_CTRL (0x51) -#define MT6360_PMU_ADC_BAT_DATA_H (0x52) -#define MT6360_PMU_ADC_BAT_DATA_L (0x53) -#define MT6360_PMU_IMID_BACKBST_ON (0x54) -#define MT6360_PMU_IMID_BACKBST_OFF (0x55) -#define MT6360_PMU_ADC_CONFIG (0x56) -#define MT6360_PMU_ADC_EN2 (0x57) -#define MT6360_PMU_ADC_IDLE_T (0x58) -#define MT6360_PMU_ADC_RPT_1 (0x5A) -#define MT6360_PMU_ADC_RPT_2 (0x5B) -#define MT6360_PMU_ADC_RPT_3 (0x5C) -#define MT6360_PMU_ADC_RPT_ORG1 (0x5D) -#define MT6360_PMU_ADC_RPT_ORG2 (0x5E) -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) -#define MT6360_PMU_CHG_CTRL19 (0x61) -#define MT6360_PMU_VDDASUPPLY (0x62) -#define MT6360_PMU_BC12_MANUAL (0x63) -#define MT6360_PMU_CHGDET_FUNC (0x64) -#define MT6360_PMU_FOD_CTRL (0x65) -#define MT6360_PMU_CHG_CTRL20 (0x66) -#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) -#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) -#define MT6360_PMU_RESV2 (0x69) -#define MT6360_PMU_USBID_CTRL1 (0x6D) -#define MT6360_PMU_USBID_CTRL2 (0x6E) -#define MT6360_PMU_USBID_CTRL3 (0x6F) -#define MT6360_PMU_FLED_CFG (0x70) -#define MT6360_PMU_RESV3 (0x71) -#define MT6360_PMU_FLED1_CTRL (0x72) -#define MT6360_PMU_FLED_STRB_CTRL (0x73) -#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) -#define MT6360_PMU_FLED1_TOR_CTRL (0x75) -#define MT6360_PMU_FLED2_CTRL (0x76) -#define MT6360_PMU_RESV4 (0x77) -#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) -#define MT6360_PMU_FLED2_TOR_CTRL (0x79) -#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) -#define MT6360_PMU_FLED_VMID_RTM (0x7B) -#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) -#define MT6360_PMU_FLED_PWSEL (0x7D) -#define MT6360_PMU_FLED_EN (0x7E) -#define MT6360_PMU_FLED_Hidden1 (0x7F) -#define MT6360_PMU_RGB_EN (0x80) -#define MT6360_PMU_RGB1_ISNK (0x81) -#define MT6360_PMU_RGB2_ISNK (0x82) -#define MT6360_PMU_RGB3_ISNK (0x83) -#define MT6360_PMU_RGB_ML_ISNK (0x84) -#define MT6360_PMU_RGB1_DIM (0x85) -#define MT6360_PMU_RGB2_DIM (0x86) -#define MT6360_PMU_RGB3_DIM (0x87) -#define MT6360_PMU_RESV5 (0x88) -#define MT6360_PMU_RGB12_Freq (0x89) -#define MT6360_PMU_RGB34_Freq (0x8A) -#define MT6360_PMU_RGB1_Tr (0x8B) -#define MT6360_PMU_RGB1_Tf (0x8C) -#define MT6360_PMU_RGB1_TON_TOFF (0x8D) -#define MT6360_PMU_RGB2_Tr (0x8E) -#define MT6360_PMU_RGB2_Tf (0x8F) -#define MT6360_PMU_RGB2_TON_TOFF (0x90) -#define MT6360_PMU_RGB3_Tr (0x91) -#define MT6360_PMU_RGB3_Tf (0x92) -#define MT6360_PMU_RGB3_TON_TOFF (0x93) -#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) -#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) -#define MT6360_PMU_RESV6 (0x97) -#define MT6360_PMU_SPARE1 (0x9A) -#define MT6360_PMU_SPARE2 (0xA0) -#define MT6360_PMU_SPARE3 (0xB0) -#define MT6360_PMU_SPARE4 (0xC0) -#define MT6360_PMU_CHG_IRQ1 (0xD0) -#define MT6360_PMU_CHG_IRQ2 (0xD1) -#define MT6360_PMU_CHG_IRQ3 (0xD2) -#define MT6360_PMU_CHG_IRQ4 (0xD3) -#define MT6360_PMU_CHG_IRQ5 (0xD4) -#define MT6360_PMU_CHG_IRQ6 (0xD5) -#define MT6360_PMU_QC_IRQ (0xD6) -#define MT6360_PMU_FOD_IRQ (0xD7) -#define MT6360_PMU_BASE_IRQ (0xD8) -#define MT6360_PMU_FLED_IRQ1 (0xD9) -#define MT6360_PMU_FLED_IRQ2 (0xDA) -#define MT6360_PMU_RGB_IRQ (0xDB) -#define MT6360_PMU_BUCK1_IRQ (0xDC) -#define MT6360_PMU_BUCK2_IRQ (0xDD) -#define MT6360_PMU_LDO_IRQ1 (0xDE) -#define MT6360_PMU_LDO_IRQ2 (0xDF) -#define MT6360_PMU_CHG_STAT1 (0xE0) -#define MT6360_PMU_CHG_STAT2 (0xE1) -#define MT6360_PMU_CHG_STAT3 (0xE2) -#define MT6360_PMU_CHG_STAT4 (0xE3) -#define MT6360_PMU_CHG_STAT5 (0xE4) -#define MT6360_PMU_CHG_STAT6 (0xE5) -#define MT6360_PMU_QC_STAT (0xE6) -#define MT6360_PMU_FOD_STAT (0xE7) -#define MT6360_PMU_BASE_STAT (0xE8) -#define MT6360_PMU_FLED_STAT1 (0xE9) -#define MT6360_PMU_FLED_STAT2 (0xEA) -#define MT6360_PMU_RGB_STAT (0xEB) -#define MT6360_PMU_BUCK1_STAT (0xEC) -#define MT6360_PMU_BUCK2_STAT (0xED) -#define MT6360_PMU_LDO_STAT1 (0xEE) -#define MT6360_PMU_LDO_STAT2 (0xEF) -#define MT6360_PMU_CHG_MASK1 (0xF0) -#define MT6360_PMU_CHG_MASK2 (0xF1) -#define MT6360_PMU_CHG_MASK3 (0xF2) -#define MT6360_PMU_CHG_MASK4 (0xF3) -#define MT6360_PMU_CHG_MASK5 (0xF4) -#define MT6360_PMU_CHG_MASK6 (0xF5) -#define MT6360_PMU_QC_MASK (0xF6) -#define MT6360_PMU_FOD_MASK (0xF7) -#define MT6360_PMU_BASE_MASK (0xF8) -#define MT6360_PMU_FLED_MASK1 (0xF9) -#define MT6360_PMU_FLED_MASK2 (0xFA) -#define MT6360_PMU_FAULTB_MASK (0xFB) -#define MT6360_PMU_BUCK1_MASK (0xFC) -#define MT6360_PMU_BUCK2_MASK (0xFD) -#define MT6360_PMU_LDO_MASK1 (0xFE) -#define MT6360_PMU_LDO_MASK2 (0xFF) -#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) - -/* MT6360_PMU_IRQ_SET */ -#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) -#define MT6360_IRQ_RETRIG BIT(2) - -#define CHIP_VEN_MASK (0xF0) -#define CHIP_VEN_MT6360 (0x50) -#define CHIP_REV_MASK (0x0F) - -#endif /* __MT6360_H__ */ diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h index 949268581b36..56f210eebc54 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -13,6 +13,7 @@ enum chip_id { MT6323_CHIP_ID = 0x23, MT6358_CHIP_ID = 0x58, + MT6359_CHIP_ID = 0x59, MT6391_CHIP_ID = 0x91, MT6397_CHIP_ID = 0x97, }; diff --git a/include/linux/mfd/mt6397/rtc.h b/include/linux/mfd/mt6397/rtc.h index c3748b53bf7d..068ae1c0f0e8 100644 --- a/include/linux/mfd/mt6397/rtc.h +++ b/include/linux/mfd/mt6397/rtc.h @@ -36,6 +36,7 @@ #define RTC_AL_MASK_DOW BIT(4) #define RTC_TC_SEC 0x000a +#define RTC_TC_MTH_MASK 0x000f /* Min, Hour, Dom... register offset to RTC_TC_SEC */ #define RTC_OFFSET_SEC 0 #define RTC_OFFSET_MIN 1 diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index e07f6e61cd38..a96e6d43ca06 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -437,6 +437,87 @@ enum rk809_reg_id { #define RK817_RTC_COMP_LSB_REG 0x10 #define RK817_RTC_COMP_MSB_REG 0x11 +/* RK817 Codec Registers */ +#define RK817_CODEC_DTOP_VUCTL 0x12 +#define RK817_CODEC_DTOP_VUCTIME 0x13 +#define RK817_CODEC_DTOP_LPT_SRST 0x14 +#define RK817_CODEC_DTOP_DIGEN_CLKE 0x15 +#define RK817_CODEC_AREF_RTCFG0 0x16 +#define RK817_CODEC_AREF_RTCFG1 0x17 +#define RK817_CODEC_AADC_CFG0 0x18 +#define RK817_CODEC_AADC_CFG1 0x19 +#define RK817_CODEC_DADC_VOLL 0x1a +#define RK817_CODEC_DADC_VOLR 0x1b +#define RK817_CODEC_DADC_SR_ACL0 0x1e +#define RK817_CODEC_DADC_ALC1 0x1f +#define RK817_CODEC_DADC_ALC2 0x20 +#define RK817_CODEC_DADC_NG 0x21 +#define RK817_CODEC_DADC_HPF 0x22 +#define RK817_CODEC_DADC_RVOLL 0x23 +#define RK817_CODEC_DADC_RVOLR 0x24 +#define RK817_CODEC_AMIC_CFG0 0x27 +#define RK817_CODEC_AMIC_CFG1 0x28 +#define RK817_CODEC_DMIC_PGA_GAIN 0x29 +#define RK817_CODEC_DMIC_LMT1 0x2a +#define RK817_CODEC_DMIC_LMT2 0x2b +#define RK817_CODEC_DMIC_NG1 0x2c +#define RK817_CODEC_DMIC_NG2 0x2d +#define RK817_CODEC_ADAC_CFG0 0x2e +#define RK817_CODEC_ADAC_CFG1 0x2f +#define RK817_CODEC_DDAC_POPD_DACST 0x30 +#define RK817_CODEC_DDAC_VOLL 0x31 +#define RK817_CODEC_DDAC_VOLR 0x32 +#define RK817_CODEC_DDAC_SR_LMT0 0x35 +#define RK817_CODEC_DDAC_LMT1 0x36 +#define RK817_CODEC_DDAC_LMT2 0x37 +#define RK817_CODEC_DDAC_MUTE_MIXCTL 0x38 +#define RK817_CODEC_DDAC_RVOLL 0x39 +#define RK817_CODEC_DDAC_RVOLR 0x3a +#define RK817_CODEC_AHP_ANTI0 0x3b +#define RK817_CODEC_AHP_ANTI1 0x3c +#define RK817_CODEC_AHP_CFG0 0x3d +#define RK817_CODEC_AHP_CFG1 0x3e +#define RK817_CODEC_AHP_CP 0x3f +#define RK817_CODEC_ACLASSD_CFG1 0x40 +#define RK817_CODEC_ACLASSD_CFG2 0x41 +#define RK817_CODEC_APLL_CFG0 0x42 +#define RK817_CODEC_APLL_CFG1 0x43 +#define RK817_CODEC_APLL_CFG2 0x44 +#define RK817_CODEC_APLL_CFG3 0x45 +#define RK817_CODEC_APLL_CFG4 0x46 +#define RK817_CODEC_APLL_CFG5 0x47 +#define RK817_CODEC_DI2S_CKM 0x48 +#define RK817_CODEC_DI2S_RSD 0x49 +#define RK817_CODEC_DI2S_RXCR1 0x4a +#define RK817_CODEC_DI2S_RXCR2 0x4b +#define RK817_CODEC_DI2S_RXCMD_TSD 0x4c +#define RK817_CODEC_DI2S_TXCR1 0x4d +#define RK817_CODEC_DI2S_TXCR2 0x4e +#define RK817_CODEC_DI2S_TXCR3_TXCMD 0x4f + +/* RK817_CODEC_DI2S_CKM */ +#define RK817_I2S_MODE_MASK (0x1 << 0) +#define RK817_I2S_MODE_MST (0x1 << 0) +#define RK817_I2S_MODE_SLV (0x0 << 0) + +/* RK817_CODEC_DDAC_MUTE_MIXCTL */ +#define DACMT_MASK (0x1 << 0) +#define DACMT_ENABLE (0x1 << 0) +#define DACMT_DISABLE (0x0 << 0) + +/* RK817_CODEC_DI2S_RXCR2 */ +#define VDW_RX_24BITS (0x17) +#define VDW_RX_16BITS (0x0f) + +/* RK817_CODEC_DI2S_TXCR2 */ +#define VDW_TX_24BITS (0x17) +#define VDW_TX_16BITS (0x0f) + +/* RK817_CODEC_AMIC_CFG0 */ +#define MIC_DIFF_MASK (0x1 << 7) +#define MIC_DIFF_DIS (0x0 << 7) +#define MIC_DIFF_EN (0x1 << 7) + #define RK817_POWER_EN_REG(i) (0xb1 + (i)) #define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i)) diff --git a/include/linux/mfd/rsmu.h b/include/linux/mfd/rsmu.h new file mode 100644 index 000000000000..6870de608233 --- /dev/null +++ b/include/linux/mfd/rsmu.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Core interface for Renesas Synchronization Management Unit (SMU) devices. + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ + +#ifndef __LINUX_MFD_RSMU_H +#define __LINUX_MFD_RSMU_H + +/* The supported devices are ClockMatrix, Sabre and SnowLotus */ +enum rsmu_type { + RSMU_CM = 0x34000, + RSMU_SABRE = 0x33810, + RSMU_SL = 0x19850, +}; + +/** + * + * struct rsmu_ddata - device data structure for sub devices. + * + * @dev: i2c/spi device. + * @regmap: i2c/spi bus access. + * @lock: mutex used by sub devices to make sure a series of + * bus access requests are not interrupted. + * @type: RSMU device type. + * @page: i2c/spi bus driver internal use only. + */ +struct rsmu_ddata { + struct device *dev; + struct regmap *regmap; + struct mutex lock; + enum rsmu_type type; + u16 page; +}; +#endif /* __LINUX_MFD_RSMU_H */ diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index f1631a39acfc..f92fe090473d 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -67,11 +67,8 @@ struct sec_pmic_dev { struct i2c_client *i2c; unsigned long device_type; - int irq_base; int irq; struct regmap_irq_chip_data *irq_data; - - bool wakeup; }; int sec_irq_init(struct sec_pmic_dev *sec_pmic); @@ -81,15 +78,8 @@ int sec_irq_resume(struct sec_pmic_dev *sec_pmic); struct sec_platform_data { struct sec_regulator_data *regulators; struct sec_opmode_data *opmode; - int device_type; int num_regulators; - int irq_base; - int (*cfg_pmic_irq)(void); - - bool wakeup; - bool buck_voltage_lock; - int buck_gpios[3]; int buck_ds[3]; unsigned int buck2_voltage[8]; @@ -99,35 +89,12 @@ struct sec_platform_data { unsigned int buck4_voltage[8]; bool buck4_gpiodvs; - int buck_set1; - int buck_set2; - int buck_set3; - int buck2_enable; - int buck3_enable; - int buck4_enable; int buck_default_idx; - int buck2_default_idx; - int buck3_default_idx; - int buck4_default_idx; - int buck_ramp_delay; - int buck2_ramp_delay; - int buck34_ramp_delay; - int buck5_ramp_delay; - int buck16_ramp_delay; - int buck7810_ramp_delay; - int buck9_ramp_delay; - int buck24_ramp_delay; - int buck3_ramp_delay; - int buck7_ramp_delay; - int buck8910_ramp_delay; - - bool buck1_ramp_enable; bool buck2_ramp_enable; bool buck3_ramp_enable; bool buck4_ramp_enable; - bool buck6_ramp_enable; int buck2_init; int buck3_init; diff --git a/include/linux/mfd/wcd934x/registers.h b/include/linux/mfd/wcd934x/registers.h index bb8d2e276668..76a943c83c63 100644 --- a/include/linux/mfd/wcd934x/registers.h +++ b/include/linux/mfd/wcd934x/registers.h @@ -18,6 +18,8 @@ #define WCD934X_EFUSE_SENSE_STATE_DEF 0x10 #define WCD934X_EFUSE_SENSE_EN_MASK BIT(0) #define WCD934X_EFUSE_SENSE_ENABLE BIT(0) +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 0x002a +#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 0x002b #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037 #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038 #define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039 @@ -103,21 +105,58 @@ #define WCD934X_ANA_AMIC3 0x0610 #define WCD934X_ANA_AMIC4 0x0611 #define WCD934X_ANA_MBHC_MECH 0x0614 +#define WCD934X_MBHC_L_DET_EN_MASK BIT(7) +#define WCD934X_MBHC_L_DET_EN BIT(7) +#define WCD934X_MBHC_GND_DET_EN_MASK BIT(6) +#define WCD934X_MBHC_MECH_DETECT_TYPE_MASK BIT(5) +#define WCD934X_MBHC_MECH_DETECT_TYPE_INS 1 +#define WCD934X_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) +#define WCD934X_MBHC_HPHL_PLUG_TYPE_NO 1 +#define WCD934X_MBHC_GND_PLUG_TYPE_MASK BIT(3) +#define WCD934X_MBHC_GND_PLUG_TYPE_NO 1 +#define WCD934X_MBHC_HSL_PULLUP_COMP_EN BIT(2) +#define WCD934X_MBHC_HSG_PULLUP_COMP_EN BIT(1) +#define WCD934X_MBHC_HPHL_100K_TO_GND_EN BIT(0) #define WCD934X_ANA_MBHC_ELECT 0x0615 +#define WCD934X_ANA_MBHC_BIAS_EN_MASK BIT(0) +#define WCD934X_ANA_MBHC_BIAS_EN BIT(0) #define WCD934X_ANA_MBHC_ZDET 0x0616 #define WCD934X_ANA_MBHC_RESULT_1 0x0617 #define WCD934X_ANA_MBHC_RESULT_2 0x0618 #define WCD934X_ANA_MBHC_RESULT_3 0x0619 +#define WCD934X_ANA_MBHC_BTN0 0x061a +#define WCD934X_VTH_MASK GENMASK(7, 2) +#define WCD934X_ANA_MBHC_BTN1 0x061b +#define WCD934X_ANA_MBHC_BTN2 0x061c +#define WCD934X_ANA_MBHC_BTN3 0x061d +#define WCD934X_ANA_MBHC_BTN4 0x061e +#define WCD934X_ANA_MBHC_BTN5 0x061f +#define WCD934X_ANA_MBHC_BTN6 0x0620 +#define WCD934X_ANA_MBHC_BTN7 0x0621 +#define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2) #define WCD934X_ANA_MICB1 0x0622 #define WCD934X_MICB_VAL_MASK GENMASK(5, 0) #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6) +#define WCD934X_MICB_DISABLE 0 +#define WCD934X_MICB_ENABLE 1 +#define WCD934X_MICB_PULL_UP 2 +#define WCD934X_MICB_PULL_DOWN 3 #define WCD934X_ANA_MICB_PULL_UP 0x80 #define WCD934X_ANA_MICB_ENABLE 0x40 #define WCD934X_ANA_MICB_DISABLE 0x0 #define WCD934X_ANA_MICB2 0x0623 +#define WCD934X_ANA_MICB2_ENABLE BIT(6) +#define WCD934X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6) +#define WCD934X_ANA_MICB2_VOUT_MASK GENMASK(5, 0) +#define WCD934X_ANA_MICB2_RAMP 0x0624 +#define WCD934X_RAMP_EN_MASK BIT(7) +#define WCD934X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2) #define WCD934X_ANA_MICB3 0x0625 #define WCD934X_ANA_MICB4 0x0626 #define WCD934X_BIAS_VBG_FINE_ADJ 0x0629 +#define WCD934X_MBHC_CTL_CLK 0x0656 +#define WCD934X_MBHC_CTL_BCS 0x065a +#define WCD934X_MBHC_STATUS_SPARE_1 0x065b #define WCD934X_MICB1_TEST_CTL_1 0x066b #define WCD934X_MICB1_TEST_CTL_2 0x066c #define WCD934X_MICB2_TEST_CTL_1 0x066e @@ -141,7 +180,11 @@ #define WCD934X_HPH_CNP_WG_CTL 0x06cc #define WCD934X_HPH_GM3_BOOST_EN_MASK BIT(7) #define WCD934X_HPH_GM3_BOOST_ENABLE BIT(7) +#define WCD934X_HPH_CNP_WG_TIME 0x06cd #define WCD934X_HPH_OCP_CTL 0x06ce +#define WCD934X_HPH_PA_CTL2 0x06d2 +#define WCD934X_HPHPA_GND_R_MASK BIT(6) +#define WCD934X_HPHPA_GND_L_MASK BIT(4) #define WCD934X_HPH_L_EN 0x06d3 #define WCD934X_HPH_GAIN_SRC_SEL_MASK BIT(5) #define WCD934X_HPH_GAIN_SRC_SEL_COMPANDER 0 @@ -152,6 +195,8 @@ #define WCD934X_HPH_OCP_DET_MASK BIT(0) #define WCD934X_HPH_OCP_DET_ENABLE BIT(0) #define WCD934X_HPH_OCP_DET_DISABLE 0 +#define WCD934X_HPH_R_ATEST 0x06d8 +#define WCD934X_HPHPA_GND_OVR_MASK BIT(1) #define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea #define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb #define WCD934X_CLK_SYS_MCLK_PRG 0x0711 @@ -172,7 +217,19 @@ #define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e #define WCD934X_SIDO_RIPPLE_FREQ_EN_MASK BIT(0) #define WCD934X_SIDO_RIPPLE_FREQ_ENABLE BIT(0) +#define WCD934X_MBHC_NEW_CTL_1 0x0720 +#define WCD934X_MBHC_CTL_RCO_EN_MASK BIT(7) +#define WCD935X_MBHC_CTL_RCO_EN BIT(7) #define WCD934X_MBHC_NEW_CTL_2 0x0721 +#define WCD934X_M_RTH_CTL_MASK GENMASK(3, 2) +#define WCD934X_MBHC_NEW_PLUG_DETECT_CTL 0x0722 +#define WCD934X_HSDET_PULLUP_C_MASK GENMASK(7, 6) +#define WCD934X_MBHC_NEW_ZDET_ANA_CTL 0x0723 +#define WCD934X_ZDET_RANGE_CTL_MASK GENMASK(3, 0) +#define WCD934X_ZDET_MAXV_CTL_MASK GENMASK(6, 4) +#define WCD934X_MBHC_NEW_ZDET_RAMP_CTL 0x0724 +#define WCD934X_MBHC_NEW_FSM_STATUS 0x0725 +#define WCD934X_MBHC_NEW_ADC_RESULT 0x0726 #define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727 #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733 #define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735 |