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| author | Sonny Rao <sonnyrao@chromium.org> | 2014-10-16 09:58:05 -0700 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2014-11-10 12:40:35 +0100 |
| commit | 536f6b91d21b81bec6c8a675b3a00052ee05f986 (patch) | |
| tree | c9e998819fd46fc6a64bd0b12bcfcf7cef86a511 /include/linux/platform_data | |
| parent | 390e316c606de2f839389698f4531004cfe1bafd (diff) | |
| download | cachepc-linux-536f6b91d21b81bec6c8a675b3a00052ee05f986.tar.gz cachepc-linux-536f6b91d21b81bec6c8a675b3a00052ee05f986.zip | |
mmc: dw_mmc: Reset DMA before enabling IDMAC
We've already got a reset of DMA after it's done. Add one before we
start DMA too. This fixes a data corruption on Rockchip SoCs which
will get bad data when doing a DMA transfer after doing a PIO transfer.
We tested this on an Exynos 5800 with HS200 and didn't notice any
difference in sequential read throughput.
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'include/linux/platform_data')
0 files changed, 0 insertions, 0 deletions