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| author | Sasha Neftin <sasha.neftin@intel.com> | 2020-06-02 10:50:47 +0300 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2020-06-29 18:21:09 -0700 |
| commit | 707abf0695481ad19b0b74af65f30c71123d6154 (patch) | |
| tree | b97226e58ca75d8c5a3a5bf7b8f48bf936766554 /include/linux/platform_data | |
| parent | 93ec439abeefe2e205657ae2b98a7fee4fbd4a0b (diff) | |
| download | cachepc-linux-707abf0695481ad19b0b74af65f30c71123d6154.tar.gz cachepc-linux-707abf0695481ad19b0b74af65f30c71123d6154.zip | |
igc: Add initial LTR support
The LTR message on the PCIe inform the requested latency
on which the PCIe must become active to the downstream
PCIe port of the system.
This patch provide recommended LTR parameters by i225
specification.
Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'include/linux/platform_data')
0 files changed, 0 insertions, 0 deletions