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authorSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>2022-04-19 20:05:16 -0500
committerSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>2022-07-13 17:27:24 -0500
commit11585682dee921e2fa667490a8ce2931de6236a7 (patch)
treed712abad23a92f05338a8205476fe6426a9e4318 /include/linux/timerqueue.h
parentc99c52483f74d4f080490120c90d415687905088 (diff)
downloadcachepc-linux-11585682dee921e2fa667490a8ce2931de6236a7.tar.gz
cachepc-linux-11585682dee921e2fa667490a8ce2931de6236a7.zip
iommu/amd: Set translation valid bit only when IO page tables are in use
On AMD system with SNP enabled, IOMMU hardware checks the host translation valid (TV) and guest translation valid (GV) bits in the device table entry (DTE) before accessing the corresponded page tables. However, current IOMMU driver sets the TV bit for all devices regardless of whether the host page table is in use. This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which do not the host page table root pointer set up. Thefore, when SNP is enabled, only set TV bit when DMA remapping is not used, which is when domain ID in the AMD IOMMU device table entry (DTE) is zero. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Diffstat (limited to 'include/linux/timerqueue.h')
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