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| author | Anshuman Gupta <anshuman.gupta@intel.com> | 2019-10-03 13:47:38 +0530 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2019-10-08 11:05:30 +0300 |
| commit | 41286861b4c9abdb4e0b32c6caa0967780e6f803 (patch) | |
| tree | a1d9d47ede5529280fd66752e4f5369f07fe66dd /include/linux/timerqueue.h | |
| parent | 1c4d821db919366034dc9ff4c01b4b0da0b8e30f (diff) | |
| download | cachepc-linux-41286861b4c9abdb4e0b32c6caa0967780e6f803.tar.gz cachepc-linux-41286861b4c9abdb4e0b32c6caa0967780e6f803.zip | |
drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
v1: comment modification for DMC_DBUG3.
using GEN >= 12 check instead of IS_TIGERLAKE()
to print DMC_DEBUG3 counter value.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191003081738.22101-7-anshuman.gupta@intel.com
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions