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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-07-06 17:08:20 +0530 |
|---|---|---|
| committer | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-07-13 17:27:23 -0500 |
| commit | aced2ea70b45759ca2d67d06de74169e454032b5 (patch) | |
| tree | 08902c541a6c96dbe93dfbe3f7451acb182e0dc5 /include/linux/timerqueue.h | |
| parent | e2528db7d306263be0cb4872b2c638d43d808bcb (diff) | |
| download | cachepc-linux-aced2ea70b45759ca2d67d06de74169e454032b5.tar.gz cachepc-linux-aced2ea70b45759ca2d67d06de74169e454032b5.zip | |
iommu/amd: Include PCI segment ID when initialize IOMMU
Extend current device ID variables to 32-bit to include the 16-bit
segment ID when parsing device information from IVRS table to initialize
each IOMMU.
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20220706113825.25582-31-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions