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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2021-03-14 18:14:51 +0000 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2021-04-07 08:36:36 +0100 |
| commit | c13ab9457fbbe67dbc1b1296ede05cccb812b81e (patch) | |
| tree | b9409ab3506d7de2fb21c4b21e7e0c57f84ab67d /include/linux/timerqueue.h | |
| parent | 0c4c4a868ab4af5886d070379b5964d1e0835c19 (diff) | |
| download | cachepc-linux-c13ab9457fbbe67dbc1b1296ede05cccb812b81e.tar.gz cachepc-linux-c13ab9457fbbe67dbc1b1296ede05cccb812b81e.zip | |
staging:iio:cdc:ad7150: Timeout register covers both directions so both need updating
The timeout is treated as one single value, but the datasheet describes
it as two 4 bit values, one for each direction of event.
As such change the driver to support the separate directions.
Also add limit checking to ensure it fits within the 4 bits.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210314181511.531414-5-jic23@kernel.org
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions