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| author | Vasant Hegde <vasant.hegde@amd.com> | 2022-07-06 17:07:52 +0530 |
|---|---|---|
| committer | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-07-13 17:27:19 -0500 |
| commit | cef63d68dc6e44297b48b7b201372632029ab40e (patch) | |
| tree | cbb8f654b5fda4830ffc997b0223036834951438 /include/uapi/linux/errqueue.h | |
| parent | d3747c8748f8f8744f4d16cfbc8cb2a9242a9ba4 (diff) | |
| download | cachepc-linux-cef63d68dc6e44297b48b7b201372632029ab40e.tar.gz cachepc-linux-cef63d68dc6e44297b48b7b201372632029ab40e.zip | |
iommu/amd: Introduce pci segment structure
Newer AMD systems can support multiple PCI segments, where each segment
contains one or more IOMMU instances. However, an IOMMU instance can only
support a single PCI segment.
Current code assumes that system contains only one pci segment (segment 0)
and creates global data structures such as device table, rlookup table,
etc.
Introducing per PCI segment data structure, which contains segment
specific data structures. This will eventually replace the global
data structures.
Also update `amd_iommu->pci_seg` variable to point to PCI segment
structure instead of PCI segment ID.
Co-developed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Link: https://lore.kernel.org/r/20220706113825.25582-3-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/uapi/linux/errqueue.h')
0 files changed, 0 insertions, 0 deletions