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| author | Olof Johansson <olof@lixom.net> | 2014-07-19 14:59:07 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2014-07-19 14:59:07 -0700 |
| commit | 4e9816d012dbc28dc89559261c6ffbf8ffc440dd (patch) | |
| tree | dee9f8b31f3d6d2fb141541da88e1cc1329b017e /include/uapi/linux/serial_core.h | |
| parent | da98f44f27d81d7fe9a41f69af4fe08c18d13b56 (diff) | |
| parent | 1795cd9b3a91d4b5473c97f491d63892442212ab (diff) | |
| download | cachepc-linux-4e9816d012dbc28dc89559261c6ffbf8ffc440dd.tar.gz cachepc-linux-4e9816d012dbc28dc89559261c6ffbf8ffc440dd.zip | |
Merge tag 'v3.16-rc5' into next/fixes-non-critical
Linux 3.16-rc5
Diffstat (limited to 'include/uapi/linux/serial_core.h')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index b47dba2c1e6f..5820269aa132 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -211,7 +211,7 @@ /* VIA VT8500 SoC */ #define PORT_VT8500 97 -/* Xilinx PSS UART */ +/* Cadence (Xilinx Zynq) UART */ #define PORT_XUARTPS 98 /* Atheros AR933X SoC */ @@ -238,4 +238,10 @@ /* Tilera TILE-Gx UART */ #define PORT_TILEGX 106 +/* MEN 16z135 UART */ +#define PORT_MEN_Z135 107 + +/* SC16IS74xx */ +#define PORT_SC16IS7XX 108 + #endif /* _UAPILINUX_SERIAL_CORE_H */ |