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| author | Jeremy Fertic <jeremyfertic@gmail.com> | 2018-12-11 17:55:02 -0700 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2018-12-16 14:05:56 +0000 |
| commit | 32f228cb2ac7ce46cbc3dc0188ea94157039c69a (patch) | |
| tree | c4d05e4ea774fd258e2232365153b82d0f261cc5 /include/uapi/linux | |
| parent | 9f287a1c3fffbc10360d7490f5361fff0255a93d (diff) | |
| download | cachepc-linux-32f228cb2ac7ce46cbc3dc0188ea94157039c69a.tar.gz cachepc-linux-32f228cb2ac7ce46cbc3dc0188ea94157039c69a.zip | |
staging: iio: adt7316: change interpretation of write to dac update mode
Based on the output of adt7316_show_all_DAC_update_modes() and
adt7316_show_DAC_update_mode(), adt7316_store_DAC_update_mode() should
expect the user to enter an integer input from 0 to 3. The user input is
currently expected to account for the actual bit positions in the register.
For example, choosing option 3 would require a write of 0x30 (actually 48
since it expects base 10). To address this inconsistency, create a shift
macro to be used in the valid input check as well as the calculation for
the register write.
Signed-off-by: Jeremy Fertic <jeremyfertic@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'include/uapi/linux')
0 files changed, 0 insertions, 0 deletions