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| author | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-15 11:56:07 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-15 11:56:07 -0600 |
| commit | 8f417ca9ebfa8701a41db64f5ed9cbb01b8e4219 (patch) | |
| tree | 897b28da87379412b084c895174b7b84ee3efcb2 /include/uapi/linux | |
| parent | ca0ef7fecc881a7e8d11db2d8852ab580cd29e03 (diff) | |
| parent | a142f4d3e5c54db5e942fa6ee5f3dc0e8c83207b (diff) | |
| download | cachepc-linux-8f417ca9ebfa8701a41db64f5ed9cbb01b8e4219.tar.gz cachepc-linux-8f417ca9ebfa8701a41db64f5ed9cbb01b8e4219.zip | |
Merge branch 'pci/aspm' into next
* pci/aspm:
PCI/ASPM: Add comment about L1 substate latency
PCI/ASPM: Configure L1 substate settings
PCI/ASPM: Calculate and save the L1.2 timing parameters
PCI/ASPM: Read and set up L1 substate capabilities
PCI/ASPM: Add support for L1 substates
PCI/ASPM: Add L1 substate capability structure register definitions
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 174d1147081b..f48d06e2bb4d 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -682,6 +682,7 @@ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ +#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM @@ -985,4 +986,19 @@ #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ +/* L1 PM Substates */ +#define PCI_L1SS_CAP 4 /* capability register */ +#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */ +#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ +#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */ +#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */ +#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */ +#define PCI_L1SS_CTL1 8 /* Control Register 1 */ +#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */ +#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ +#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */ +#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */ +#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F +#define PCI_L1SS_CTL2 0xC /* Control Register 2 */ + #endif /* LINUX_PCI_REGS_H */ |