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| author | Imre Deak <imre.deak@intel.com> | 2016-07-01 16:40:04 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-07-19 20:34:38 +0300 |
| commit | e419899b7c19ef99e340e2b1ba585d82fd28c53b (patch) | |
| tree | 075559619560eb25a51a896b61bedebb1867b7d1 /include/uapi | |
| parent | 62f90b38f3326206ea53f7cf4ea4616028419d60 (diff) | |
| download | cachepc-linux-e419899b7c19ef99e340e2b1ba585d82fd28c53b.tar.gz cachepc-linux-e419899b7c19ef99e340e2b1ba585d82fd28c53b.zip | |
drm/i915/gen9: Clean up MOCS table definitions
Use named struct initializers for clarity. Also fix the target cache
definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0
meant ELLC but on GEN9+ it means the TC and LRU controls are taken from
the PTE.
No functional change, igt/gem_mocs_settings still passing after this
change.
v2: (Chris)
- Add back the hexa literals for the entries.
Add note that igt/gem_mocs_settings still passes.
CC: Rong R Yang <rong.r.yang@intel.com>
CC: Yakui Zhao <yakui.zhao@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467380406-11954-2-git-send-email-imre.deak@intel.com
Diffstat (limited to 'include/uapi')
0 files changed, 0 insertions, 0 deletions