Merge tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Meson8b: Updates and fixup HDMI and video clocks
- Meson8b: Fixup reset polarity
- Meson gx and g12: fix GPU glitch free mux switch

* tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
  clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: g12a: Prepare the GPU clock tree to change at runtime
  clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
  clk: meson: meson8b: make the hdmi_sys clock tree mutable
  clk: meson8b: export the HDMI system clock

1 files changed, 1 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 68862aaf977e..4c5965ae1df4 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -107,6 +107,7 @@
 #define CLKID_PERIPH		126
 #define CLKID_AXI		128
 #define CLKID_L2_DRAM		130
+#define CLKID_HDMI_SYS		174
 #define CLKID_VPU		190
 #define CLKID_VDEC_1		196
 #define CLKID_VDEC_HCODEC	199