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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-10-09 16:04:24 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-10 10:14:42 +0100 |
| commit | 9d41318c4e43da6b4c95a21cf366bf18179291fd (patch) | |
| tree | e5443de08e2d47f317c15d5839c3f254e9fe4f95 /include | |
| parent | ba2c74da52eba388d959a1000a9dd08fa4857659 (diff) | |
| download | cachepc-linux-9d41318c4e43da6b4c95a21cf366bf18179291fd.tar.gz cachepc-linux-9d41318c4e43da6b4c95a21cf366bf18179291fd.zip | |
drm/i915/tgl: simplify the lrc register list for !RCS
There are small differences between the blitter and the video engines in
the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
blitter). Since we never explicitly set a value for those register and
given that we don't need to update the offsets in the lrc image when we
change engine within the class for virtual engine because the HW can
handle that, instead of having a separate define for the BCS we can
just restrict the programming to the part we're interested in, which is
common across the engines.
Bspec: 45584
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191009230424.6507-2-daniele.ceraolospurio@intel.com
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions