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| author | David S. Miller <davem@davemloft.net> | 2020-07-05 15:25:59 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-07-05 15:25:59 -0700 |
| commit | dbacfd8ca755b9f710ab17a1e47572fc4e5dabcc (patch) | |
| tree | 830c899a6be455557058bc2753daece86a104cde /include | |
| parent | e1f04670440442b6218b391b5f822819fb3b8c6f (diff) | |
| parent | 7e14a2dc8c656acea48729daf3f617aa76d62937 (diff) | |
| download | cachepc-linux-dbacfd8ca755b9f710ab17a1e47572fc4e5dabcc.tar.gz cachepc-linux-dbacfd8ca755b9f710ab17a1e47572fc4e5dabcc.zip | |
Merge branch 'Phylink-integration-improvements-for-Felix-DSA-driver'
Vladimir Oltean says:
====================
Phylink integration improvements for Felix DSA driver
This is an overhaul of the Felix switch driver's phylink operations.
Patches 1, 3, 4 and 5 are cleanup, patch 2 is adding a new feature and
and patch 6 is adaptation to the new format of an existing phylink API
(mac_link_up).
Changes since v2:
- Replaced "PHYLINK" with "phylink".
- Rewrote commit message of patch 5/6.
Changes since v1:
- Now using phy_clear_bits and phy_set_bits instead of plain writes to
MII_BMCR. This combines former patches 1/7 and 6/7 into a single new
patch 1/6.
- Updated commit message of patch 5/6.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/fsl/enetc_mdio.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/fsl/enetc_mdio.h b/include/linux/fsl/enetc_mdio.h index 4875dd38af7e..2d9203314865 100644 --- a/include/linux/fsl/enetc_mdio.h +++ b/include/linux/fsl/enetc_mdio.h @@ -15,6 +15,7 @@ #define ENETC_PCS_IF_MODE_SGMII_EN BIT(0) #define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1) #define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2)) +#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3) /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS |