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authorNicholas Piggin <npiggin@gmail.com>2017-05-21 23:15:45 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2017-06-20 22:21:59 +1000
commit4d7cd3b956713d3dfbc3028ad1251b3f6b416a53 (patch)
tree7d37213be774ecae2911253bf88cebd8fa1bcf72 /scripts/patch-kernel
parentfe5482c04312791bb19202e47f8a7751d476251e (diff)
downloadcachepc-linux-4d7cd3b956713d3dfbc3028ad1251b3f6b416a53.tar.gz
cachepc-linux-4d7cd3b956713d3dfbc3028ad1251b3f6b416a53.zip
powerpc/64s: Avoid r3 save/restore in SLB miss handler
The SLB miss handler uses r3 for the faulting address but r12 is mostly able to be freed up to save r3 in. It just requires SRR1 be reloaded again on error. It would be more conventional to use r12 for SRR1 (and use r11 to save r3), but slb_allocate_realmode clobbers r11 and not r12. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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