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| author | Sharat Masetty <smasetty@codeaurora.org> | 2018-09-27 22:16:22 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-10-03 20:24:54 -0400 |
| commit | 9fb4bfd0be010371d3fdd2280e9d99f315382379 (patch) | |
| tree | 0f9aa5738480512e3593cfd321869bf70e8bc133 /scripts/stackusage | |
| parent | b689a830f5264e3a53307ba468e376e9f95f15e0 (diff) | |
| download | cachepc-linux-9fb4bfd0be010371d3fdd2280e9d99f315382379.tar.gz cachepc-linux-9fb4bfd0be010371d3fdd2280e9d99f315382379.zip | |
drm/msm/a6xx: Send the right perf index value to GMU
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions