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| author | Vishal Sagar <vishal.sagar@xilinx.com> | 2020-05-27 15:57:18 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-06-23 13:09:46 +0200 |
| commit | 9e5eb9a451837946d93e077e0bf02bfcd203e4be (patch) | |
| tree | 8f7ae48f9f1cec15a7abb767c5a48a577d3d7953 /scripts | |
| parent | b3a9e3b9622ae10064826dccb4f7a52bd88c7407 (diff) | |
| download | cachepc-linux-9e5eb9a451837946d93e077e0bf02bfcd203e4be.tar.gz cachepc-linux-9e5eb9a451837946d93e077e0bf02bfcd203e4be.zip | |
media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
D-PHY in Rx mode and a Video Format Bridge.
[Fix indentation error in if...then...else]
[Fix number of cells in reg property]
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions