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| author | Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> | 2020-04-07 21:34:39 +0800 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2020-04-15 13:13:39 +0200 |
| commit | 35eba185fd1a3c61556a3050edbddc58d953303f (patch) | |
| tree | 8a9384dda5d9f930ec0106dc1fba8c0433ab9dc9 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 85f8fcaeed33315e19905af23f2693a81956688a (diff) | |
| download | cachepc-linux-35eba185fd1a3c61556a3050edbddc58d953303f.tar.gz cachepc-linux-35eba185fd1a3c61556a3050edbddc58d953303f.zip | |
i2c: designware: Calculate SCL timing parameter for High Speed Mode
Custom parameters for HCNT/LCNT are not available for OF based system.
Thus, we will use existing SCL timing parameter calculation functions
for High Speed Mode too.
The value for the parameters tSYMBOL and tLOW is taken from DesignWare
DW_apb_i2c Databook v2.01a, section 3.15.4.6. The calculation should
assume higher bus load since it gives slower timing parameter.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
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