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| author | Todor Tomov <todor.tomov@linaro.org> | 2018-07-25 12:38:16 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-08-02 06:11:19 -0400 |
| commit | 5ba913b3fca8579d43c24d220d2f579cf3e992af (patch) | |
| tree | f1cbc90f1ac70507f80226c6077d266fcd406f4d /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 2004fc09b34128182ed26ec7b8f28190e5189061 (diff) | |
| download | cachepc-linux-5ba913b3fca8579d43c24d220d2f579cf3e992af.tar.gz cachepc-linux-5ba913b3fca8579d43c24d220d2f579cf3e992af.zip | |
media: camss: csiphy: Ensure clock mux config is done before the rest
Add a write memory barier after clock mux config and before the rest
of the csiphy config.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Hans Verkuil <hansverk@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions