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| author | Ken Chalmers <ken.chalmers@amd.com> | 2017-12-14 12:44:39 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:17:18 -0500 |
| commit | 6d5d346f0462c1921877b260379115d21f6269c9 (patch) | |
| tree | bebb7c06547ce13d08d98e6b430c58c7b07b43bc /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 73535feb175d7ec570911b1f00aa11e30cb7e92e (diff) | |
| download | cachepc-linux-6d5d346f0462c1921877b260379115d21f6269c9.tar.gz cachepc-linux-6d5d346f0462c1921877b260379115d21f6269c9.zip | |
drm/amd/display: Eliminate several Maximus-specific code paths
This allows Maximus emulation to more closely mirror actual silicon
execution.
* Enable pool->base.display_clock creation on Maximus.
* Enable rest of dce110_apply_ctx_to_hw on Maximus.
* Remove apply_ctx_to_hw_fpga (no longer necessary with the full
dce110_apply_ctx_to_hw enabled).
* Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock
for Maximus (this was the only fix-up necessary after enabling
dce110_apply_ctx_to_hw; everything else works unmodified on
Maximus).
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions