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| author | Karthik B S <karthik.b.s@intel.com> | 2020-09-21 16:32:06 +0530 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-09-28 14:12:49 +0300 |
| commit | 0bbca6097d501c8484f3ab4199b6dea457c4c489 (patch) | |
| tree | d7e858002602897745073e03f4ac56c3b57d6298 /tools/perf/scripts/python/bin | |
| parent | 30ff93af9e19dbe88ff8b5e711e05b26b991eec0 (diff) | |
| download | cachepc-linux-0bbca6097d501c8484f3ab4199b6dea457c4c489.tar.gz cachepc-linux-0bbca6097d501c8484f3ab4199b6dea457c4c489.zip | |
drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once every few flips.
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -No need of irq disable if we are not doing vblank evade. (Ville)
v8: -Rebased.
v9: -Move the return in intel_pipe_update_end before tracepoint. (Ville)
v10: Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-5-karthik.b.s@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions