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| author | Pramod Kumar <pramod.kumar@broadcom.com> | 2018-06-01 17:56:08 -0700 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2018-06-26 15:40:12 -0700 |
| commit | a0061fc283bc4f8ac5f7f4b717ca089100124518 (patch) | |
| tree | 6142ff0c67d71429394dc6e72933450c092fe1f3 /tools/perf/scripts/python/bin | |
| parent | 8dd970a2cd7fcca44acec30aaaeee19f1e2bd6de (diff) | |
| download | cachepc-linux-a0061fc283bc4f8ac5f7f4b717ca089100124518.tar.gz cachepc-linux-a0061fc283bc4f8ac5f7f4b717ca089100124518.zip | |
arm64: dts: Update Stingray clock DT nodes
Update clock output names in the Stingray clock DT nodes so they match
the binding document and the latest ASIC datasheet. Also add entries
for LCPLL2
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions