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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-04-28 16:01:33 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-05-22 10:39:24 +0200 |
| commit | 2f227605394bbab75511d54f0773e9dbe2976ee3 (patch) | |
| tree | d53ee45fff896112be89f64944a6de030394f97c /tools/perf/scripts/python/netdev-times.py | |
| parent | cdbbd26f482b569b9c3a3b49887699f7a956d4e0 (diff) | |
| download | cachepc-linux-2f227605394bbab75511d54f0773e9dbe2976ee3.tar.gz cachepc-linux-2f227605394bbab75511d54f0773e9dbe2976ee3.zip | |
pinctrl: armada-37xx: Add irqchip support
The Armada 37xx SoCs can handle interrupt through GPIO. However it can
only manage the edge ones.
The way the interrupt are managed is classical so we can use the generic
interrupt chip model.
The only unusual "feature" is that many interrupts are connected to the
parent interrupt controller. But we do not take advantage of this and use
the chained irq with all of them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions