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| author | hersen wu <hersenxs.wu@amd.com> | 2019-04-10 15:17:40 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:10 -0500 |
| commit | b37727fb148612ca11568a8c83c143e1d991571c (patch) | |
| tree | 3f9a96bb620454d6350c0674f3aa9dc82ee7458b /tools/perf/scripts/python/stackcollapse.py | |
| parent | c92b4c46c164fbc05b72543b76222b8468f9fad3 (diff) | |
| download | cachepc-linux-b37727fb148612ca11568a8c83c143e1d991571c.tar.gz cachepc-linux-b37727fb148612ca11568a8c83c143e1d991571c.zip | |
drm/amd/display: Add vupdate interrupt sources to NV10
[WHY] linux upstream already has interrupt vupdate for freesync
in dcn10. dcn20 interrupt shares the same source code as dcn10.
but dcn20 interrupt translator does not add vupdate interrupt.
this cause index of vupdate aarray be negative which causes
crash.
[HOW] add vupdate into dc interrupt transltor
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions