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| author | Thierry Reding <treding@nvidia.com> | 2017-10-12 16:29:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-15 10:12:32 +0100 |
| commit | 2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8 (patch) | |
| tree | 2f0e111f2fb5f4797a8bce773f122053278c5ca2 /tools/perf/scripts/python | |
| parent | 02b0cc52c0c3c89641276cb1e7abddd35e036923 (diff) | |
| download | cachepc-linux-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.tar.gz cachepc-linux-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.zip | |
memory: tegra: Create SMMU display groups
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210.
This allows the display controllers on these devices to share the same
IOMMU domain using the standard IOMMU group mechanism.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions