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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-01-25 10:18:21 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-02-11 11:15:22 +0100 |
| commit | 325b820fa97f40704439674421a55b443810938d (patch) | |
| tree | cf5bf1bf85aca1af6bd832cbe099c5b6104f2409 /tools/perf/scripts/python | |
| parent | 3d8d3504d23351bcbab7be08f82c5dfabc3c9e0a (diff) | |
| download | cachepc-linux-325b820fa97f40704439674421a55b443810938d.tar.gz cachepc-linux-325b820fa97f40704439674421a55b443810938d.zip | |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20220125161821.1951906-3-dinguyen@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions