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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2019-03-07 10:12:24 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-03-28 02:09:57 +0900
commit415a0729bd1225f0ffbc0ba82888dd65772554f7 (patch)
tree3391d12659b560aacdc57ab5015f653da999c2af /tools/perf/scripts/python
parentb49f6d83e290f17e20f4e5cf31288d3bb4955ea6 (diff)
downloadcachepc-linux-415a0729bd1225f0ffbc0ba82888dd65772554f7.tar.gz
cachepc-linux-415a0729bd1225f0ffbc0ba82888dd65772554f7.zip
misc: fastrpc: make sure memory read and writes are visible
dma_alloc_coherent buffers could have writes queued in store buffers so commit them before sending buffer to DSP using correct dma barriers. Same with vice-versa. Fixes: c68cfb718c8f ("misc: fastrpc: Add support for context Invoke method") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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