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authorAlex Deucher <alexander.deucher@amd.com>2018-01-05 10:25:57 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:17:14 -0500
commitb1d128689f9c602a3dbea37b47a27a568d55754d (patch)
tree6e7f5703c0ed9a28b140017fc3fc3bd0504a9cc4 /tools/perf/scripts/python
parent73c732405fddfe16b122c77de83397289463b557 (diff)
downloadcachepc-linux-b1d128689f9c602a3dbea37b47a27a568d55754d.tar.gz
cachepc-linux-b1d128689f9c602a3dbea37b47a27a568d55754d.zip
drm/amdgpu: adjust HDP write queue flushing for tlb invalidation
Separate tlb invalidation and hdp flushing and move the HDP flush to the caller. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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