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| author | Wenjing Liu <Wenjing.Liu@amd.com> | 2019-04-25 12:11:50 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:12 -0500 |
| commit | cba4d59c936cd17ac601c188725ccd779467a509 (patch) | |
| tree | b095ab895117e3b635d6d49976d4b92503ded507 /tools/perf/scripts/python | |
| parent | e34fe1bba65880c5dd66fae11362bd5c370493c1 (diff) | |
| download | cachepc-linux-cba4d59c936cd17ac601c188725ccd779467a509.tar.gz cachepc-linux-cba4d59c936cd17ac601c188725ccd779467a509.zip | |
drm/amd/display: fix a potential issue in DSC logic
[why]
In compute dsc bandwidth range there is an uninitialized variable
[how]
Initialize the variable to the correct value.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions