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| author | Ludovic Barre <ludovic.barre@st.com> | 2018-10-08 14:08:44 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-10-09 09:13:04 +0200 |
| commit | daf9713c5ef8c3ffb0bdf7de11b53b2b2756c4f1 (patch) | |
| tree | 68df91f5c84948d8988210fd0a7349c5c020635b /tools/perf/scripts/python | |
| parent | c931d495cd3d5f01eba5da958207d37c63edbf10 (diff) | |
| download | cachepc-linux-daf9713c5ef8c3ffb0bdf7de11b53b2b2756c4f1.tar.gz cachepc-linux-daf9713c5ef8c3ffb0bdf7de11b53b2b2756c4f1.zip | |
mmc: mmci: expand startbiterr to irqmask and error check
All variants don't pretend to have a startbiterr.
-While data error check, if status register return an error
(like MCI_DATACRCFAIL) we must avoid to check MCI_STARTBITERR
(if not desired).
-expand start_err to MCI_IRQENABLE to avoid to set this bit by default.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions